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ISL36411 датащи(PDF) 3 Page - Intersil Corporation |
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ISL36411 датащи(HTML) 3 Page - Intersil Corporation |
3 / 12 page ISL36411 3 FN6965.1 March 25, 2010 Pin Functions and Definitions PIN NAME PIN NUMBER DESCRIPTION VDD 1, 5, 9, 13, 24, 27, 28, 31, 32, 35, 36, 39 Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. IN1[P, N] 2, 3 Equalizer 1 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. LOSB1 4 LOS BAR indicator 1. Low output when IN1 signal is below DT threshold. IN2[P, N] 6, 7 Equalizer 2 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. LOSB2 8 LOS BAR indicator 2. Low output when IN2 signal is below DT threshold. IN3[P, N] 10, 11 Equalizer 3 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. LOSB3 12 LOS BAR indicator 3. Low output when IN3 signal is below DT threshold. IN4[P, N] 14, 15 Equalizer 4 differential input, CML. the use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. LOSB4 16 LOS BAR indicator 4. Low output when IN4 signal is below DT threshold. GND 17, 23, 40, 46 These pins should be grounded. DT2 18 Detection Threshold for equalizers 3 and 4. Reference DC voltage threshold for input signal power detection. Data output OUT3 and OUT4 are muted when the power of IN3 and IN4, respectively, fall below the threshold. Tie to ground to disable electrical idle preservation and always enable the limiting amplifier. CP2[A,B] 19, 20 Control pins for setting equalizers 3 and 4. CMOS logic inputs. Pins are read as a 2-digit number to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25kΩ resistor. NC 21, 22, 41, 45 not connected: do not make any connections to these pins. OUT4[N, P] 25, 26 Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. OUT3[N, P] 29, 30 Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. OUT2[N, P] 33, 34 Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. OUT1[N, P] 37, 38 Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. CP1[B, A] 42, 43 Control pins for setting equalizers 1 and 2. CMOS logic inputs. Pins are read as a 2-digit number to set the boost level. A is the MSB, and B is the LSB. Pins are internally pulled down through a 25kΩ resistor. DT1 44 Detection Threshold for equalizers 1 and 2. Reference DC voltage threshold for input signal power detection. Data output OUT1 and OUT2 are muted when the power of IN1 and IN2, respectively, fall below the threshold. Tie to ground to disable electrical idle preservation and always enable the limiting amplifier. Exposed Pad - Exposed ground pad. For proper electrical and thermal performance, this pad should be connected to the PCB ground plane. |
Аналогичный номер детали - ISL36411 |
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Аналогичное описание - ISL36411 |
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