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ISL6113IRZA датащи(PDF) 4 Page - Intersil Corporation |
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ISL6113IRZA датащи(HTML) 4 Page - Intersil Corporation |
4 / 24 page 4 FN6457.0 September 25, 2007 Pin Descriptions PIN NAME FUNCTION 9, 28 FORCE_ONA, FORCE_ONB Asserting a FORCE_ON input low will turn on the MAIN and AUX supplies to the respective slot in a forced mode over riding the ON input and the UV, OC and short circuit protections on those outputs. UVLO protection for the VSTBY input is not affected by the FORCE_ON pins. Asserting FORCE_ON will cause the PWRGD and FAULT outputs to enter their open-drain state. This input is internally pulled high to the VAUX rail. Functionality is disabled when PRSNT is high. 44, 43 ONA, ONB Enable input for MAIN outputs use to enable or disable MAIN voltage supply (12V and 3.3V) outputs. Taking ONX low after a fault resets the respective slots Main Output Fault Latch. Functionality is disabled when PRSNT is high. 45, 42 AUXENA, AUXENB 3.3VAUX Enable Input, enables the respective VAUX output. Pulling AUXENX low after a fault resets the associated slot’s VAUX fault latch. Functionality is disabled when PRSNT is high. 5, 32 12VINA,12VINB Connect to 12VMAIN supply and high side of sense resistor. This is one of two pins for Kelvin connection to measure the 50mV CR Vth. An undervoltage lockout prevents the IC main supply function until 12VIN >10V. The current regulation threshold is set by connecting a sense resistor between this pin and 12VSENSE. When the current-limit threshold of IR = 50mV is reached, the 12VGATE pin is modulated to maintain a constant 50mV voltage across the sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is maintained for CR duration, the circuit breaker is tripped and both GATE pins for the affected slot turn off the switch FETs and thus turn off the supplies to the slot. 8, 29 12VSENSEA, 12VSENSEB 12V current sense low side input. This is the second of two pins for Kelvin connection to the RSENSE to measure the 50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and associated 12VIN pin. 10, 27 12VOUTA, 12VOUTB 12V output voltage monitor for UV condition. This is the voltage input downstream of the MOSFET that is delivered to the add-in card load. 12, 25 3VINA, 3VINB Connect to 3VMAIN supply and high side of sense resistor. This provides one of two pins for Kelvin connection to measure the 50mV CR Vth. Undervoltage lockout (UVLO) prevents turn-on until 3VIN >2.75V. The current regulation threshold is set by connecting a sense resistor between this pin and 3VSENSE. When the current-limit threshold of IR = 50mV is reached, the 3VGATE pin is modulated to maintain a constant 50mV voltage across the sense resistor and thereby a constant current is passed into the load. If the 50mV threshold is maintained for the CR duration, the circuit breaker is tripped and both FETs for the affected slot are turned-off. 13, 24 3VSENSEA, 3VSENSEB 3.3V current sense low side input. This provides the second of two pins for Kelvin connection for measuring the 50mV CR Vth. The CR limits are set by connecting a sense resistor between each of these pins and associated 3VINX pin. 16, 21 3VOUTA, 3VOUTB 3.3V output voltage monitor for UV condition. This is the voltage downstream of the MOSFET that is delivered to the add-in card load. 1, 36 FAULTA, FAULTB An open drain output which is pulled low whenever the CR duration has expired due to an OC fault condition on any of the MAIN or the AUX supplies or in the event of an IC over-temperature condition. If fault latch is invoked by a MAIN (+12V, +3.3V) supply fault, then it is reset by pulling the faulted slot’s ON pin low. if fault was asserted because of an OC fault condition on the slot’s AUX output then pulling the AUXEN input low will reset the latch. Both enabling inputs must be pulled low to clear a fault condition on both the MAIN and VAUX outputs of the same slot. Internal over-temperature limit is ~+140°C with a +20°C hysteresis. 15, 22 VAUXA, VAUXB 3.3VAUX output to the PCI-E slot: This output connects to the VAUX pin of the PCI-E connector through an internal 0.3 Ω FET. This output is current regulated to ~1A. 11, 26 VSTBYA VSTBYB 3.3V bias input for the IC, and internal VAUX switches. VVSTBY must always be present for proper IC bias, either from a dedicated 3.3V or 3VMAIN if AUX supply not implemented. 41 L/R Latch-off or Retry bar input. Tying this input low invokes a periodic retry to turn-on after current regulation timer has expired on both slots. Leaving this pin open provides a latch-off operational mode after CR period has expired. In this mode turn-on is initiated by cycling the appropriate EN input(s). This pin is internally pulled up to VSTBY. 40, 39 PRSNTA, PRSNTB The card presence detection input disables the operation of the FORCE_ON, ON and AUXEN inputs if not pulled to GND. If after turn-on, the PRSNT input goes high then all associated outputs (MAIN and AUX) are turned off immediately. 6, 31 PWRGDA, PWRGDB A POWER GOOD NOT signal that is asserted low while all output voltages are compliant. 4, 38 GPI_A0, GPI_B0 ~5ms debounced user attention input, driven by either a mechanical switch or digital signal form higher level controller. 48, 47 GPO_A0, GPO_B0 User attention output, that can be used to drive LEDs, alarms or other attention getting devices. Open drain with 90mA pull-down capability. ISL6113, ISL6114 |
Аналогичный номер детали - ISL6113IRZA |
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Аналогичное описание - ISL6113IRZA |
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