74AHC_AHCT573_5

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Product data sheet

Rev. 05 — 25 March 2010

4 of 19

NXP Semiconductors

74AHC573; 74AHCT573

Octal D-type transparant latch; 3-state

5.

Pinning information

5.1 Pinning

5.2 Pin description

Fig 5.

Pin configuration SO20 and TSSOP20

Fig 6.

Pin configuration DHVQFN20

573

OE

D0

Q0

D1

Q1

D2

Q2

D3

Q3

D4

Q4

D5

Q5

D6

Q6

D7

Q7

GND

LE

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1

2

3

4

5

6

7

8

9

10

12

11

14

13

16

15

18

17

20

19

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74AHC573

74AHCT573

Transparent top view

Q7

D6

D7

Q6

D5

Q5

D4

Q4

D3

Q3

D2

Q2

D1

Q1

D0

Q0

9

12

8

13

7

14

6

15

5

16

4

17

3

18

2

19

terminal 1

index area

Table 2.

Pin description

Symbol

Pin

Description

OE

1

output enable input (active LOW)

D0 to D7

2, 3, 4, 5, 6, 7, 8, 9

data input

GND

10

ground (0 V)

LE

11

latch enable (active HIGH)

Q0 to Q7

19, 18, 17, 16, 15, 14, 13, 12

data output

20

supply voltage