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AD8376ACPZ-R7 датащи(PDF) 6 Page - Analog Devices

номер детали AD8376ACPZ-R7
подробное описание детали  Ultralow Distortion IF Dual VGA
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD8376ACPZ-R7 датащи(HTML) 6 Page - Analog Devices

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AD8376
Rev. A | Page 6 of 24
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
A2
2
A3
3
A4
4
VCMA
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO GROUND.
SOLDER TO A LOW IMPEDANCE GROUND PLANE.
5
VCMB
6
B4
7
B3
8
B2
24 OPA+
23 OPA–
22 ENBA
21 GNDA
20 GNDB
19 ENBB
18 OPB–
17 OPB+
AD8376
TOP VIEW
(Not to Scale)
Figure 3. 32-Lead LFCSP
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
A2
MSB − 2 for the Gain Control Interface for Channel A.
2
A3
MSB − 1 for the Gain Control Interface for Channel A.
3
A4
MSB for the 5-Bit Gain Control Interface for Channel A.
4
VCMA
Channel A Input Common-Mode Voltage. Typically bypassed to ground through capacitor.
5
VCMB
Channel B Input Common-Mode Voltage. Typically bypassed to ground through capacitor.
6
B4
MSB for the 5-Bit Gain Control Interface for Channel B.
7
B3
MSB − 1 for the Gain Control Interface for Channel B.
8
B2
MSB − 2 for the Gain Control Interface for Channel B.
9
B1
LSB + 1 for the Gain Control Interface for Channel B.
10
B0
LSB for the Gain Control Interface for Channel B.
11
IPB+
Channel B Positive Input.
12
IPB−
Channel B Negative Input.
13, 20
GNDB
Device Common (DC Ground) for Channel B.
14
VCCB
Positive Supply Pin for Channel B. Should be bypassed to ground using suitable bypass capacitor.
15, 17
OPB+
Positive Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal.
16, 18
OPB−
Negative Output Pins (Open Collector) for Channel B. Require dc bias of +5 V nominal.
19
ENBB
Power Enable Pin for Channel B. Channel B is enabled with a logic high and disabled with a logic low.
21, 28
GNDA
Device Common (DC Ground) for Channel A.
22
ENBA
Power Enable Pin for Channel A. Channel A is enabled with a logic high and disabled with a logic low.
23, 25
OPA−
Negative Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal.
24, 26
OPA+
Positive Output Pins (Open Collector) for Channel A. Require dc bias of +5 V nominal.
27
VCCA
Positive Supply Pins for Channel A. Should be bypassed to ground using suitable bypass capacitor.
29
IPA−
Channel A Negative Input.
30
IPA+
Channel A Positive Input.
31
A0
LSB for the Gain Control Interface for Channel A.
32
A1
LSB + 1 for the Gain Control Interface for Channel A.
Exposed Pad
Internally connected to ground. Solder to a low impedance ground plane.


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