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ISL25700 датащи(PDF) 6 Page - Intersil Corporation

номер детали ISL25700
подробное описание детали  Programmable Temperature Controlled MOSFET Driver
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производитель  INTERSIL [Intersil Corporation]
домашняя страница  http://www.intersil.com/cda/home
Logo INTERSIL - Intersil Corporation

ISL25700 датащи(HTML) 6 Page - Intersil Corporation

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ISL25700
6
FN6885.0
September 3, 2010
VDAC_OFFSET Offset
DAC register set to 0, No load
0
0.2
1
LSB
(Note 7)
ROUT
DAC Output Impedance
350
Ω
PSRR
Power Supply Rejection Ratio DAC at middle scale, frequency
from 0Hz to 25kHz
-85
dB
TCV
(Notes 10,
11)
Temperature Coefficient
DAC register set between 20 hex
and FF hex
±45
ppm/°C
Analog Specifications Over recommended operating conditions unless otherwise stated. Boldface limits apply over
the operating temperature range, -40°C to +125°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 6)
MAX
(Note 13) UNITS
Operating Specifications Over the recommended operating conditions unless otherwise specified. Boldface limits
apply over the operating temperature range, -40°C to +125°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 13)
TYP
(Note 6)
MAX
(Note 13) UNITS
IDD1
VDD Supply Current
(Non-Volatile Write/read)
fSCL = 400kHz; SDA = Open;
(for I2C, Active, Read and Write
States) IPMOS = 0mA, DAC unload
4
mA
IDD2
VDD Supply Current
(Volatile Write/read)
IPMOS = 0mA, DAC unload
2.8
mA
ILkgDig
Leakage Current, at SDA and
SCL Pins
Voltage at pin from GND to VCC
-2
2
μA
tDAC
(Note 11)
DAC Settling Time
From bus STOP condition to VDAC
change
3
μs
VPOR
Power-On Recall Voltage
Minimum VDD at which memory recall
occurs
2.5
2.9
V
VDD Ramp VDD Ramp Rate
@ any level from 0V to 15V
0.2
50
V/ms
tD
(Note 11)
Power-Up Delay
VDD above VPOR, to DAC Register recall
completed, and I2C Interface in
standby state
1
ms
EEPROM SPECIFICATIONS
EEPROM Endurance
10,000
Cycles
EEPROM Retention
Temperature ≤ +55°C
50
Years
Temperature ≤ +125°C
10
Years
SERIAL INTERFACE SPECIFICATIONS
VI2C
I2C Bus Voltage
VI2C ≤ VDD
2.7
5.5
V
VIL
SDA, and SCL Input Buffer
LOW Voltage
VI2C from 2.7V to 5.5V
0.8
V
VIH
SDA, and SCL Input Buffer
HIGH Voltage
VI2C from 2.7V to 5.5V
1.4
V
Hysteresis
(Note 11)
SDA and SCL Input Buffer
Hysteresis
0.05*VI2C
V
VOL
(Note 11)
SDA Output Buffer LOW
Voltage, Sinking 4mA
0
0.4
V
Cpin
(Note 11)
SDA, and SCL Pin Capacitance
10
pF
fSCL
SCL Frequency
400
kHz
tIN
(Note 11)
Pulse Width Suppression Time
at SDA and SCL Inputs
Any pulse narrower than the max spec
is suppressed
50
ns


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