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LC651102F датащи(PDF) 11 Page - Sanyo Semicon Device

номер детали LC651102F
подробное описание детали  On-Chip UVEPROM 4-Bit Single-Chip Microcontroller
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производитель  SANYO [Sanyo Semicon Device]
домашняя страница  https://www.sanyo-av.com/us/
Logo SANYO - Sanyo Semicon Device

LC651102F датащи(HTML) 11 Page - Sanyo Semicon Device

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No. 5221-11/19
LC65E1104
Continued from preceding page.
Parameter
Symbol
Conditions
Ratings
Unit
min
typ
max
[Serial output]
Output delay time
tCKO
SO: Specified from the falling edge of SCK.
0.6
µs
Nch OD only, external 1k
Ω, external 50 pF, Fig. 6
[Pulse output]
Period
tPCY
64
×tCYC
µs
High-level pulse width
tPH
32
× tCYC
µs
± 10%
Low-level pulse width
tPL
32
× tCYC
µs
± 10%
[AD conversion characteristics]
Resolution
VDD = 4.7 to 5.3 V
8
bits
Absolute accuracy
AV+ = VDD, AV– = VSS, VDD = 4.7 to 5.3 V
±1
±2
LSB
AD speed 1/1, at 26
× tCYC, VDD = 4.7 to 5.3 V
72 (tCYC
312 (tCYC
Conversion time
TCAD
= 2.77 µs)
= 12 µs)
µs
AD speed 1/2, at 51
× tCYC, VDD = 4.7 to 5.3 V
141 (tCYC
612 (tCYC
= 2.77 µs)
= 12 µs)
Reference input voltage
AV+
AV+: VDD = 4.7 to 5.3 V
AV–
VDD
V
AV–
AV–: VDD = 4.7 to 5.3 V
VSS
AV+
Reference input current range
IRIF
AV+, AV–: AV+ = VDD, VDD = 4.7 to 5.3 V, AV– = VSS
75
150
300
µA
Analog input voltage range
VAIN
AD0 to AD7: VDD = 4.7 to 5.3 V
AV–
AV+
V
Port pins AD0 to AD7
1
Including output OFF leakage current. VAIN = VDD,
Analog port input current
IAIN
VDD= 4.7 to 5.3 V
µA
Port pins AD0 to AD7
VAIN = VSS, VDD= 4.7 to 5.3 V
–1
[Watchdog timer]
Cw
WDR: VDD = 3 to 6 V
0.1 ± 5%
µF
Guaranteed constant*7
Rw
WDR: VDD = 3 to 6 V
680 ± 1%
k
RI
WDR: VDD = 3 to 6 V
100 ± 1%
Clear time (discharge)
tWCT
WDR: Fig. 8, VDD = 3 to 6 V
100
µs
Clear time (charge)
tWCCY
WDR: Fig. 8, VDD = 3 to 6 V
36
ms
Cw
WDR: VDD = 4 to 6 V
0.047 ± 5%
µF
Guaranteed constant*7
Rw
WDR: VDD = 4 to 6 V
680 ± 1%
k
RI
WDR: VDD = 4 to 6 V
100 ± 1%
Clear time (discharge)
tWCT
WDR: Fig. 8, VDD = 4 to 6 V
40
µs
Clear time (charge)
tWCCY
WDR: Fig. 8, VDD = 4 to 6 V
18
ms
PE0: Fig. 7, tCYC = 4
× system clock period,
Nch OD only, external 1 k
Ω, external 50 pF
Note: 1. The LC65E1104 will accept input voltages up to the generated oscillator amplitude if the oscillator circuit in figure 4 with circuit constants in the
guaranteed constants ranges is driven from within the IC.
2. Average over a 100 ms period
3. The operating supply voltage VDD must be held until standby mode is enterd after the execution of a HALT instruction. The PA3 pin must be free
from chattering during the HALT instruction cycle.
4. The OSC1 pin input circuit has Schmitt trigger characteristics when the 2-terminal RC oscillator option or the external clock oscillator option is
selected.
5. fCFOSC: oscillator frequency. The center frequency of a ceramic oscillator has a tolerance range of about 1% around the nominal value specified
by the manufacturer of the oscillator element. For details, refer to the specifications of the ceramic resonator.
6. TCYC = 4
× system clock period
7. If the LC65E1104 is used in an environment subject to condensation, leakage between PE1 and adjacent pins and leakage associated with
external RCA circuits require special attention.


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