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LC7537NE датащи(PDF) 4 Page - Sanyo Semicon Device |
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LC7537NE датащи(HTML) 4 Page - Sanyo Semicon Device |
4 / 11 page No. 2169-4/11 LC7537N, 7537AN, 7537NE Pin No. Symbol Description of Functions Remarks 8(2) L-VSS 35(35) R-VSS 42(42) INIT 22(20) CE 20(16) DI 21(17) CLK 1(43) VDD 23(21) VCC 19(15) VSS 24(22) VEE 2(3, 7) 41(18, 30, NC 34, 41, 44) (19) VDD(NC) Main volume control block fader control common terminals. The impedance of pattern connected to these pins should be as low as possible. Since L–VSS (R–VSS) and VSS have not been connected inside the LSI, they should be connected together on the outside in conformance with their individual specifications. Particular attenuation should be paid to the capacitance assigned to the capacitors put between L–VSS (R–VSS) and VSS, which will emerge as a residual resistive component when control is turned down for maximum attenuation. Intra-IC latch resetting terminal Control-setting data at the internal latch will be indeterminate when power has just been switched on, so that by engaging the “L” level of this pin at power-on, the fader control may be set at its – ∞ position and muting behaviour is engaged (Note: V DD to VEE Level). Chip enable terminal. When this pin is made “H” to “L”, data is written in the internal latch, activating the various analog switches. When the “H” level is then restored, transfer of the data will be enabled. Input terminals for serial data and clock that serve control purposes. Continued from preceding page. These pins are connected to the relevant power supplies. Exercise caution against VCC rising earlier than VDD. No connect pins. Absolutely nothing should be connected here. LC7537AN and LC7537NE only VDD subterminal. Connected to VDD or left open. |
Аналогичный номер детали - LC7537NE |
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Аналогичное описание - LC7537NE |
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