LC07424LP

No.A1619-10/32

VDDio=VDDdig=1.71 to 3.6V, VSSvh=VSSh=VSSana=VSSsp=VSSv=VSSdig=0V

Parameter

Symbol

Conditions

min

typ

max

unit

ADC block LPF fs=44.1kHz

Passband

ADC_PB

Gain=0.05dB

20

kHz

Passband ripple

ADC_PR

0.05

dB

Stopband

ADC_SB

24.1

kHz

Stopband attenuation

ADC_SA

Input signal =24.1kHz

-61

dB

ADC block HPF fs=44.1kHz

Cutoff frequency

ADC_FC

0.882

Hz

DAC block LPF fs=44.1kHz

Passband

DAC_PB

20

kHz

Passband ripple

DAC_PR

±0.015

dB

Stopband

ADC_SB

24.1

kHz

Stopband attenuation

ADC_SA

Input signal =24.1kHz

-58

dB

DAC block HPF fs=44.1kHz

Cutoff frequency

ADC_FC

0.86

Hz

Switching Characteristics

Parameter

Symbol

Conditions

min

typ

max

unit

Microcontroller serial interface timing

SCLK Cycle time

tCYC

4T

8T

ns

SCLK high period

tSH

2T

4T

ns

SCLK low period

tSL

2T

4T

ns

Data setup time

tSU

2T

4T

ns

Data hold time

tHD

2T

4T

ns

CSX rise to SCLK wait time

tWSCLK

0T

2T

ns

SCLK to CSX rise wait time

tWCSX

4T

6T

ns

Rise time

tSR

50

ns

Fall time

tSF

50

ns

Audio data timing

Clock phase (Note 2)

tPH

75

ns

Clock phase (Note 3)

tPH

1 / (128fs)

ns

Deta delay time

tDD

0

75

ns

Data setup time

tSUA

1T

ns

Data hold time

tHDA

1T

ns

Note 1: T = 1 / fMCLK, fMCLK: Frequency of MCLKIN pin; example: when fMCLK = 10MHz, T = 100ns, 2T = 200ns

Note 2: LRCK and BCLK are inputs in Slave mode.

The MCLK timing needs only to be synchronized only with LRCK and BCLK and its phase is irrelevant.

Note 3: In master mode, LRCK and BCLK are output in master mode and fs is the sampling frequency.

Note 4: The load of output pin: 30pF.