STK22C48

Document Number: 001-51000 Rev. *D

Page 10 of 17

SRAM Write Cycle

Parameter

Description

25 ns

45 ns

Unit

Min

Max

Min

Max

Cypress

Parameter

Alt

Write cycle time

25

–

45

–

ns

Write pulse width

20

–

30

–

ns

Chip enable to end of write

20

–

30

–

ns

Data setup to end of write

10

–

15

–

ns

Data hold after end of write

0

–

0

–

ns

Address setup to end of write

20

–

30

–

ns

Address setup to start of write

0

–

0

–

ns

Address hold after end of write

0

–

0

–

ns

Write enable to output disable

–

10

–

14

ns

Output active after end of write

5

–

5

–

ns

Switching Waveforms

Figure 9. SRAM Write Cycle 1: WE Controlled [12, 13]

Figure 10. SRAM Write Cycle 2: CE Controlled [12, 13]

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

10. Measured ±200 mV from steady state output voltage.

11. If WE is Low when CE goes Low, the outputs remain in the high impedance state.

12. HSB must be high during SRAM Write cycles.

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