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BAT54 датащи(PDF) 4 Page - Fairchild Semiconductor

номер детали BAT54
подробное описание детали  Dual DDR / Dual-Output PWM Controller
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производитель  FAIRCHILD [Fairchild Semiconductor]
домашняя страница  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

BAT54 датащи(HTML) 4 Page - Fairchild Semiconductor

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© 2005 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN5026 • Rev. 1.0.8
4
Pin Definitions
Pin #
Name
Description
11
ILIM1
Current Limit 1. A resistor from this pin to GND sets the current limit.
12
SS1
Soft Start. A capacitor from this pin to GND programs the slew rate of the converter during
initialization. During initialization, this pin is charged with a 5mA current source.
17
SS2
13
DDR
DDR Mode Control. HIGH = DDR Mode. LOW = two separate regulators operating 180
degrees out of phase.
14
VIN
Input Voltage. Normally connected to the battery, providing voltage feedforward to set the
amplitude of the internal oscillator ramp. When using the IC for two-step conversion from 5V
input, connect through 100K
Ω resistor to ground, which sets the appropriate ramp gain and
synchronizes the channels 90° out of phase.
15
PG1
Power-Good Flag. An open-drain output that pulls LOW when VSEN is outside a ±10% range of
the 0.9V reference.
16
PG2 /
REF2OUT
Power-Good 2. When not in DDR Mode, open-drain output that pulls LOW when the VOUT is
out of regulation or in a fault condition.
Reference Out 2. When in DDR Mode, provides a buffered output of REF2. Typically used as
the VDDQ/2 reference.
18
ILIM2 /
REF2
Current Limit 2. When not in DDR Mode, a resistor from this pin to GND sets the current limit.
Reference for reg #2 when in DDR Mode. Typically set to VOUT1/2.
28
VCC
VCC. This pin powers the chip as well as the LDRV buffers. The IC starts to operate when
voltage on this pin exceeds 4.6V (UVLO rising) and shuts down when it drops below 4.3V
(UVLO falling).
Block Diagram
Figure 4. IC Block Diagram


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