Technical Note

BD3538F,BD3538HFN

9/10

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2010.05 - Rev.A

© 2010 ROHM Co., Ltd. All rights reserved.

0

100

200

300

400

500

600

700

800

0

25

50

75

100

125

150

Ambient Temperature：Ta(℃)

(2) 560mW

(1) 690mW

100℃

0.0

0.5

1.0

1.5

2.0

0

25

50

75

100

125

150

Ambient Temperature：Ta(℃)

(3) 0.63W

(2) 1.35W

(1) 1.75W

(1) 1 layer (copper foil density : 65％）

θ

ja=71.4℃/W

(2) 1 layer (copper foil density : 7％)

θ

ja=92.4℃/W

(3) 1 layer (copper foil density : 0.2％)

θ

ja=198.4℃/W

●

Heat Loss

Thermal design must be conducted with the operation under the conditions listed below (which are the guaranteed

temperature range requiring consideration on appropriate margins etc.):

1. Ambient temperature Ta: 100°C or lower

2. Chip junction temperature Tj: 150°C or lower

The chip junction temperature Tj can be considered as follows. See Page 2/10 for θja.

For the package has FIN at the bottoms of IC, package power depends on the connected copper foil area. Be sure to keep

the board surface area or release the heat with setting enough through holes to inside pattern.

Most of heat loss in BD3538F/HFN occurs at the output N-channel FET. The power lost is determined by multiplying the

voltage between VIN and Vo by the output current. As this IC employs the power PKG, the thermal derating characteristics

significantly depends on the pc board conditions. When designing, care must be taken to the size of a pc board to be used.

If VTT_IN = 1.8 volts, VDDQ=1.8 volts, and Io (Ave)=0.5 A, for instance, the power dissipation is determined as follows:

Power dissipation (W) = {1.8 (V) – 0.9 (V)} × 0.5 (A) = 0.4 (W)

●

Power Dissipation

◎

SOP8

◎

HSON8

(1) 70mm×70mm×1.6mm Glass-epoxy PCB

θ

j-c=181℃/W

(2) With no heat sink

θ

j-a=222℃/W