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GS4911BCNE3 датащи(PDF) 6 Page - Gennum Corporation

номер детали GS4911BCNE3
подробное описание детали  HD/SD/Graphics Clock and Timing Generator with GENLOCK
Download  119 Pages
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производитель  GENNUM [Gennum Corporation]
домашняя страница  http://www.gennum.com
Logo GENNUM - Gennum Corporation

GS4911BCNE3 датащи(HTML) 6 Page - Gennum Corporation

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GS4911B/GS4910B HD/SD/Graphics Clock and Timing
Generator with GENLOCK
Data Sheet
36655 - 5
June 2009
6 of 119
3.8.4 TIMING_OUT Pins ............................................................................................................. 71
3.9 Custom Clock Generation ........................................................................................................... 72
3.9.1 Programming a Custom Video Clock.......................................................................... 72
3.9.2 Programming a Custom Audio Clock (GS4911B only) .......................................... 73
3.10 Custom Output Timing Signal Generation ......................................................................... 74
3.10.1 Custom Input Reference ............................................................................................... 75
3.11 Extended Audio Mode for HD Demux using the Gennum Audio Core ................... 75
3.12 GSPI Host Interface ..................................................................................................................... 76
3.12.1 Command Word Description...................................................................................... 77
3.12.2 Data Read and Write Timing....................................................................................... 78
3.12.3 Configuration and Status Registers........................................................................... 79
3.13 JTAG ...............................................................................................................................................110
3.14 Device Power-Up ......................................................................................................................111
3.14.1 Power Supply Sequencing .........................................................................................111
3.15 Device Reset ................................................................................................................................111
4. Application Reference Design .............................................................................................................112
4.1 GS4911B Typical Application Circuit ...................................................................................112
4.2 GS4910B Typical Application Circuit ...................................................................................113
5. References & Relevant Standards .......................................................................................................114
6. Package & Ordering Information ........................................................................................................115
6.1 Package Dimensions ...................................................................................................................115
6.2 Solder Reflow Profiles ................................................................................................................116
6.3 Recommended PCB Footprint .................................................................................................117
6.4 Packaging Data .............................................................................................................................117
6.5 Ordering Information .................................................................................................................118
List of Figures
GS4911B Functional Block Diagram ......................................................................................................... 2
GS4910B Functional Block Diagram ......................................................................................................... 3
Figure 1-1: XTAL1 and XTAL2 Reference Circuits .............................................................................. 20
Figure 2-1: PCLK to TIMING_OUT Signal Output Timing ................................................................. 36
Figure 3-1: HD-SD Calculation .................................................................................................................. 40
Figure 3-2: Output Accuracy and Modes of Operation ..................................................................... 42
Figure 3-3: Example HSYNC, VSYNC, and FSYNC Analog Input Timing from a
Sync Separator ................................................................................................................................................ 43
Figure 3-4: Example H Blanking, V Blanking, and F Digital Input Timing from an
SDI Deserializer .............................................................................................................................................. 44
Figure 3-5: 10FID Input Timing ................................................................................................................. 45
Figure 3-6: Internal Video Genlock Block ............................................................................................. 54
Figure 3-7: Internal Audio Genlock Block ............................................................................................. 56
Figure 3-8: Default 10FID Output Timing .............................................................................................. 67
Figure 3-9: Optional 10FID Output Timing ........................................................................................... 68
Figure 3-10: AFS Output Timing ............................................................................................................... 69
Figure 3-11: USER Programmable Output Signal ................................................................................ 70


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