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LC74772V датащи(PDF) 6 Page - Sanyo Semicon Device |
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LC74772V датащи(HTML) 6 Page - Sanyo Semicon Device |
6 / 17 page Display Control Commands The display control commands have an 8-bit serial input format. Data is input LSB first. Display Control Command Table No. 5159-6/17 LC74772V First byte Second byte Command Command code Data Data D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 COMMAND 0 0 0 0 0 RST RAM OSC TST — — — — — — — — System setup 1 SYS CLR STP MOD COMMAND 1 0 0 0 1 CSYN CLK CLK CLK — — — — — — — — System setup 2 MOD POLT MOD1 MOD0 COMMAND 2 0 0 1 0 VSYN HSYN DATA ART — — — — — — — — Input control setup POLT POLT FMT FMT COMMAND 3 0 0 1 1 PORT OUT OUT OUT — — — — — — — — General-purpose port control SET P11 P10 P9 COMMAND 4 RVS BLK BLK BLK Display operation control: 0 1 0 0 ON ON 1 0 — — — — — — — — reverse video and blinking COMMAND 5 DSP DSP DSP DSP Display control: on/off settings 0 1 0 1 4 3 2 1 — — — — — — — — for each output COMMAND 6 0 1 1 0 DSPF DSP DSP DSP — — — — — — — — Output control: systems 3 and 4 SL34 RSG GSG BSG COMMAND 8 1 0 0 0 0 BKC BKC BKC BKO4 BKO4 BKO3 BKO3 BKO2 BKO2 BKO1 BKO1 Display control: border R G B F1 F0 F1 F0 F1 F0 F1 F0 COMMAND 9 1 0 0 1 VP5 VP4 VP3 VP2 VP1 VP0 HP5 HP4 HP3 HP2 HP1 HP0 Display start position COMMAND 10 1 0 1 0 LNF LNF LNF LN 0 0 LIN LIN LIN LIN LIN LIN Display line control SZ OT4 OT3 SEL 126 115 104 93 82 71 COMMAND 11 1 0 1 1 VADR VADR VADR VADR 0 0 0 HADR HADR HADR HADR HADR RAM write address 3 2 1 0 4 3 2 1 0 COMMAND 14 1 1 1 BLK RV R G B C7 C6 C5 C4 C3 C2 C1 C0 Display RAM setup data x y x Command code: (These 4 bits in the first byte identify the command.) Command 14 is recognized by the upper 3 bits. y Command data: (These bits specify the data for each command.) • For commands 0 through 7, 8 bits of data are read in. • For commands 8 through 14, 16 bits of data are read in. • If the command 2 data-1 bit (DATAFMT) was set to 1, after the first byte of a command 14 is read in, the system goes to continuous transfer mode for reading in a series of following bytes. Note: 1. If the CS pin is set high, the command state is set to the command 0 (system control setup) state. 2. If a system reset is executed from the RST pin or by a command reset, the command register is set tot 0. |
Аналогичный номер детали - LC74772V |
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Аналогичное описание - LC74772V |
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