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Document Number: 64981

S11-0975-Rev. F, 16-May-11

Vishay Siliconix

SiC769

This document is subject to change without notice.

DETAILED OPERATIONAL DESCRIPTION

PWM Input with Tristate Function

controller IC. The PWM input is designed to be compatible

with standard controllers using two state logic (H and L) and

advanced controllers that incorporate Tristate logic (H, L and

Tristate) on the PWM output. For two state logic, the PWM

input operates as follows. When PWM is driven above

turns off and the Low side turns on. For Tristate logic, the

PWM input operates as above for driving the MOSFETs.

However, there is an third state that is entered into as the

PWM output of Tristate compatible controller enters its high

impedance state during shut-down. The high impedance

state of the controller's PWM output allows the SiC769CD to

pull the PWM input into the Tristate region (see the Tristate

Voltage Threshold Diagram below). If the PWM input stays in

side and low side MOSFETs are turned off. This function

voltage swing caused by inductor ringing and saves a

Schottky diode clamp. The PWM and Tristate regions are

separated by hysteresis to prevent false triggering. The

SiC769CD incorporates PWM voltage thresholds that are

compatible with 5 V logic.

Disable (DSBL#)

In the low state, the DSBL# pin shuts down the driver IC and

disables both high-side and low-side MOSFET. In this state,

the standby current is minimized. If DSBL# is left

unconnected an internal pull-down resistor will pull the pin

Diode Emulation Mode (SMOD) Skip Mode

When SMOD pin is low the diode emulation mode is enabled.

This is a non-synchronous conversion mode that improves

light load efficiency by reducing switching losses. Conducted

losses that occur in synchronous buck regulators when

inductor current is negative are also reduced. Circuitry in the

gate drive IC detects the inductor valley current when

inductor current crosses zero and automatically stops

switching the low side MOSFET. See SMOD Operation

Diagram for additional details. This function can be also be

used for a pre-biased output voltage. If SMOD is left

unconnected, an internal pull up resistor will pull the pin up to

Thermal Shutdown Warning (THDN)

The THDN pin is an open drain signal that flags the presence

of excessive junction temperature. Connect a maximum of

20 k

 to pull this pin up to V

sensor detects the junction temperature. The temperature

threshold is 150 °C. When this junction temperature is

exceeded the THDN flag is set. When the junction

temperature drops below 135 °C the device will clear the

THDN signal. The SiC769CD does not stop operation when

the flag is set. The decision to shutdown must be made by an

external thermal control function.

This is the power input to the drain of the high-side Power

MOSFET. This pin is connected to the high power

intermediate BUS rail.

This is the output applied to the filter circuit to deliver the

regulated high output for the buck converter. The PHASE pin

to be used exclusively as the return pin for the BOOT

capacitor. A 20.2 k

 resistor is connected between GH and

PHASE to provide a discharge path for the HS MOSFET in

Circuit Board should be such that the inductance separating

differences due to inductance effects between these two pins

should not exceed 0.5 V.

the bias supply for the gate drivers. It is recommended to

separate these pins through a resistor. This creates a low

pass filtering effect to avoid coupling of high frequency gate

drive noise into the IC.

Bootstrap Circuit (BOOT)

The internal bootstrap switch and an external bootstrap

capacitor form a charge pump that supplies voltage to the

BOOT pin. An integrated bootstrap diode is incorporated so

that only an external capacitor is necessary to complete the

bootstrap circuit. Connect a boot strap capacitor with one leg

tied to BOOT pin and the other tied to PHASE pin.

Shoot-Through Protection and Adaptive Dead Time

(AST)

The SiC769CD has an internal adaptive logic to avoid shoot

through and optimize dead time. The shoot through

protection ensures that both high-side and low-side

MOSFET are not turned on the same time. The adaptive

dead time control operates as follows. When PWM input

goes high the LS gate starts to go low after a few ns. When

this signal crosses through 1.7 V the logic to switch the HS

gate on is activated. When PWM goes low the HS gate goes

low. When the HS gate-to-source drive signal crosses

through 1.7 V the logic to turn on the LS gate is activated.

This feature helps to adjust dead time as gate transitions

change with respect to output current and temperature.

Under Voltage Lockout (UVLO)

During the start up cycle, the UVLO disables the gate drive

holding high-side and low-side MOSFET gate low until the

input voltage rail has reached a point at which the logic

circuitry can be safely activated. The SiC769CD also

incorporates logic to clamp the gate drive signals to zero

when the UVLO falling edge triggers the shutdown of the

device. As an added precaution, a 20.2 k

 resistor is

connected between GH and PHASE to provide a discharge

path for the HS MOSFET.