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74ACT16833DL датащи(PDF) 1 Page - Texas Instruments |
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74ACT16833DL датащи(HTML) 1 Page - Texas Instruments |
1 / 9 page 54ACT16833, 74ACT16833 DUAL 8BIT TO 9BIT PARITY BUS TRANSCEIVERS SCAS166A − JUNE 1990 − REVISED APRIL 1996 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 D Members of the Texas Instruments Widebus Family D Inputs Are TTL-Voltage Compatible D Parity Error Flag With Parity Generator/Checker D Register for Storage of the Parity Error Flag D Flow-Through Architecture Optimizes PCB Layout D Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise D EPIC (Enhanced-Performance Implanted CMOS) 1- µm Process D 500-mA Typical Latch-Up Immunity at 125 °C D Package Options Include 300-mil Shrink Small-Outline (DL) Packages Using 25-mil Center-to-Center Pin Spacings and 380-mil Fine-Pitch Ceramic Flat (WD) Packages Using 25-mil Center-to-Center Pin Spacings description The ’ACT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY or 2PARITY is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected. The error (1ERR or 2ERR) output is configured as an open-collector output. The B-to-A parity error flag is clocked into 1ERR or 2ERR on the low-to-high transition of the clock (1CLK or 2CLK) input. 1ERR or 2ERR is cleared (set high) by taking the clear (1CLR or 2CLR) input low. The output-enable (OEA and OEB) inputs can be used to disable the device so that the buses are effectively isolated. When both OEA and OEB are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. The 74ACT16833 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and functionality of standard small-outline packages in the same printed-circuit-board area. The 54ACT16833 is characterized for operation over the full military temperature range of −55 °C to 125°C. The 74ACT16833 is characterized for operation from −40 °C to 85°C. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC and Widebus are trademarks of Texas Instruments Incorporated. 54ACT16833 . . . WD PACKAGE 74ACT16833 . . . DL PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1OEB 1CLK 1ERR GND 1A1 1A2 VCC 1A3 1A4 1A5 GND 1A6 1A7 1A8 2A1 2A2 2A3 GND 2A4 2A5 2A6 VCC 2A7 2A8 GND 2ERR 2CLK 2OEB 1OEA 1CLR 1PARITY GND 1B1 1B2 VCC 1B3 1B4 1B5 GND 1B6 1B7 1B8 2B1 2B2 2B3 GND 2B4 2B5 2B6 VCC 2B7 2B8 GND 2PARITY 2CLR 2OEA |
Аналогичный номер детали - 74ACT16833DL |
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Аналогичное описание - 74ACT16833DL |
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