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LF198WG-QMLV датащи(PDF) 7 Page - Texas Instruments |
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LF198WG-QMLV датащи(HTML) 7 Page - Texas Instruments |
7 / 20 page Electrical Characteristics (Continued) The following specifications apply unless otherwise specified. V CC = ±15V, RL = 10K Ω,V IN = 0V, CHOLD = 0.01 µF, Logic Ref- erence Pin = 0V, Logic Pin = 4V Symbol Parameter Conditions Notes Min Max Unit Sub- groups V OS (2nd Stg) 2nd Stage V OS +V CC = 3.5V, -VCC = -32.5V -35 +35 mV 1 -50 +50 mV 2, 3 +V CC = 3V, -VCC = -7V -35 +35 mV 1 -50 +50 mV 2, 3 +V CC = 32.5V, -VCC = -3.5V -35 +35 mV 1 -50 +50 mV 2, 3 +V CC = 7V, -VCC = -3V -35 +35 mV 1 -50 +50 mV 2, 3 AC Parameters The following specifcations apply unless otherwise specified. V CC = ±15V, RL = 10K Ω,V IN = 0V, CHold = 0.01 µF, Logic Refer- ence Pin = 0V, Logic Pin = 4V Symbol Parameter Conditions Notes Min Max Unit Sub- groups T AQ Acquisition Time Delta V OUT = 10V, C Hold = 1000pF 6.0 µS 4 Delta V OUT = 10V, C Hold = 0.01µF 25 µS 4 DC Parameters: Drift Values The following conditions apply to all the following parameters, unless otherwise specified. V CC = ±15V, RL = 10K Ω,V IN = 0V, C Hold = 0.01 µF, Logic Reference Pin = 0V, Logic Pin = 4V Deltas required for S-Level product ONLY. Symbol Parameters Conditions Notes Min Max Unit Sub- groups V OS Input Offset Voltage +V CC = 15V, -VCC = -15V -0.5 0.5 mV 1 I IB Input Bias Current +V CC = 15V, -VCC = -15V -2.5 2.5 nA 1 Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test conditions Note 2: The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature, TA. The maximum allowable power dissipation at any temperature is PD =(TJMAX −TA)/θJA, or the number given in the Absolute Maximum Ratings, whichever is lower. . Note 3: Although the differential voltage may not exceed the limits given, the common-mode voltage on the logic pins may be equal to the supply voltages without causing damage to the circuit. For proper logic operation, however, one of the logic pins must always be at least 2V below the positive supply and 3V above the negative supply. Note 4: Hold step is sensitive to stray capacitive coupling between input logic signals and the hold capacitor. 1 pF, for instance, will create an additional 0.5 mV step with a 5V logic swing and a 0.01µF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. Note 5: Leakage current is measured at a junction temperature of 25˚C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25˚C value for each 11˚C increase in chip temperature. Leakage is guaranteed over full input signal range. Note 6: See Definition of Terms Note 7: Human body model, 100pF discharged through 1.5K Ω Note 8: Parameter tested go no go only for Vth test. www.national.com 6 |
Аналогичный номер детали - LF198WG-QMLV |
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Аналогичное описание - LF198WG-QMLV |
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