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SN74SSTU32866AZKER датащи(PDF) 8 Page - Texas Instruments

номер детали SN74SSTU32866AZKER
подробное описание детали  25-BIT CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
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производитель  TI1 [Texas Instruments]
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SN74SSTU32866AZKER датащи(HTML) 8 Page - Texas Instruments

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SN74SSTU32866A
25BIT CONFIGURABLE REGISTERED BUFFER
WITH ADDRESSPARITY TEST
SCAS803A − JUNE 2005 − REVISED NOVEMBER 2007
8
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
parity logic diagram for 1:2 register-A configuration (positive logic); C0 = 0, C1 = 1
D
CLK
R
G2
RESET
J1
CLK
H1
CLK
Parity
Generator
11
11
D2
A2
PPO
QERR
D2−D3,
D5−D6,
D8−D14
D2−D3,
D5−D6,
D8−D14
LPS0
(internal node)
D2−D3,
D5−D6,
D8-D14
11
PAR_IN
G1
1
0
R
CLK
2−Bit
Counter
A3, T3
VREF
0
1
C0
G6
C1
G5
LPS1
(internal node)
CE
D
CLK
R
D
CLK
R
D
CLK
R
D
CLK
R
0
1
CE
Q2A−Q3A,
Q5A−Q6A,
Q8A−Q14A
11
Q2B−Q3B,
Q5B−Q6B,
Q8B−Q14B
11
Q
Q
QQ
Q


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