поискавой системы для электроныых деталей |
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TPIC84000-Q1 датащи(PDF) 11 Page - Texas Instruments |
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TPIC84000-Q1 датащи(HTML) 11 Page - Texas Instruments |
11 / 29 page Bit 63 Bit 62 Bit 61 Bit 60 Bit 2 Bit 1 Bit 0 R63 D63 R62 R61 R60 R2 R1 R0 D62 D61 D60 D2 D1 D0 NCS SCLK SDO SDI TPIC84134-Q1 www.ti.com SLDS176 – AUGUST 2010 At each falling edge of SCLK (after NCS goes low), a new control bit is serially shifted in from the SDI pin. The SPI command is decoded to determine the destination address for the associated data. After a complete frame is received, during the next low to high transition on NCS, the SPI shift register data is transferred into the internal memory at the last decoded address. Figure 6. SPI Protocol Each SPI register in TPIC84134 has a length of 56 bits. The device has two registers for data transmission, one configuration register and one control and status register (CSR). Buffers for Data Transmission The TPIC84134 has two buffers for data transmission with a size of 56 bits each, thus a maximum of 112bits can be stored. After transmission begins, in order for the telegram to be endless, the buffers must be reloaded continuously. The inactive buffer can be reloaded while the TPIC84134 is transmitting from the active buffer, and the active buffer cannot be reloaded during transmission. SPI Command Structure The encoding of the specific SPI commands is based on, and specifically limited within the SPI shift register, to 64bits. Table 2 highlights the required basic commands to be sent via SPI. The encoding is optimized to reduce the size of the digital part and to fulfill the application software preferences. One command and its associated data are sent in the same frame. Any un-specified command or frame received by TPIC84134 will take the device into an undefined state. Copyright © 2010, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): TPIC84134-Q1 |
Аналогичный номер детали - TPIC84000-Q1 |
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Аналогичное описание - TPIC84000-Q1 |
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