SN74HC273Q1

OCTAL DTYPE FLIPFLOP

WITH CLEAR

SCLS578A − MARCH 2004 − REVISED APRIL 2008

1

POST OFFICE BOX 655303

Outputs

− Buffer/Storage Registers

− Shift Registers

− Pattern Generators

description/ordering information

This circuit is a positive-edge-triggered D-type

flip-flop with a direct clear (CLR) input.

Information at the data (D) inputs meeting the setup

time requirements is transferred to the Q outputs on

the positive-going edge of the clock (CLK) pulse.

Clock triggering occurs at a particular voltage level and is not related directly to the transition time of the

positive-going pulse. When CLK is at either the high or low level, the D input has no effect at the output.

TA

PACKAGE‡

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

−40

°C to 125°C

SOIC − DW

Reel of 2000

SN74HC273QDWRQ1

HC273Q

−40

°C to 125°C

TSSOP − PW

Reel of 2000

SN74HC273QPWRQ1

HC273Q

† For the most current package and ordering information, see the Package Option Addendum at the end of

this document, or see the TI web site at http://www.ti.com.

‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR

CLK

D

OUTPUT

Q

L

X

X

L

H

↑

HH

H

↑

LL

H

L

X

Q0

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

CLR

1Q

1D

2D

2Q

3Q

3D

4D

4Q

GND

8Q

8D

7D

7Q

6Q

6D

5D

5Q

CLK

DW OR PW PACKAGE

(TOP VIEW)

Copyright

 2008, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.