TPIC1321L

3HALF HBRIDGE GATEPROTECTED LOGICLEVEL

POWER DMOS ARRAY

SLIS042 − NOVEMBER 1994

Copyright

2−1

POST OFFICE BOX 655303

POST OFFICE BOX 1443

description

The TPIC1321L is a monolithic gate-protected

logic-level power DMOS array that consists of six

electrically isolated N-channel enhancement-

mode DMOS transistors configured as 3-half

H-bridges. Each transistor features integrated

prevent gate damage in the event that an overstress condition occurs. These zener diodes also provide up to

4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series with a 1.5-k

Ω

resistor.

The TPIC1321L is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for

operation over the case temperature of − 40

°C to 125°C.

schematic

D1

DRAIN3

D3

Z1

Z3

Z4

Z6

GND

GATE3

GATE6

OUTPUT3

DRAIN1

GATE1

OUTPUT1

GATE4

Q1

Q4

Q6

Q3

D2

Z2

Z5

Q2

Q5

SOURCE6

SOURCE4

OUTPUT2

GATE5

GATE2

DRAIN2

14, 15

21, 22

23

1, 24

2

3, 4

13

11, 12

10

8, 9

5, 6

19, 20

16

17, 18

7

D4

D5

NOTE A: For correct operation, no terminal may be taken below GND.

ZC1b

ZC1a

ZC4b

ZC4a

ZC2b

ZC2a

ZC5b

ZC5a

ZC3b

ZC3a

ZC6b

ZC6a

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

OUTPUT1

GATE4

SOURCE4

SOURCE4

GND

GND

GATE5

SOURCE6

SOURCE6

GATE6

OUTPUT3

OUTPUT3

OUTPUT1

GATE1

DRAIN1

DRAIN1

DRAIN2

DRAIN2

OUTPUT2

OUTPUT2

GATE2

DRAIN3

DRAIN3

GATE3

DW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.