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SN74ALVC16821DLR датащи(PDF) 1 Page - Texas Instruments

номер детали SN74ALVC16821DLR
подробное описание детали  3.3-V 20-BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
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производитель  TI1 [Texas Instruments]
домашняя страница  http://www.ti.com
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SN74ALVC16821DLR датащи(HTML) 1 Page - Texas Instruments

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SN74ALVC16821
3.3V 20BIT BUSINTERFACE FLIPFLOP
WITH 3STATE OUTPUTS
SCAS269A − MARCH 1993 − REVISED AUGUST 1995
1
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251−1443
D Member of the Texas Instruments
Widebus
 Family
D EPIC  (Enhanced-Performance Implanted
CMOS) Submicron Process
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
D Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
D Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 20-bit bus-interface flip-flop is designed for
low-voltage (3.3-V) VCC operation; it is tested at
2.5-V, 2.7-V, and 3.3-V VCC.
The SN74ALVC16821 can be used as two 10-bit
flip-flops or one 20-bit flip-flop. The 20 flip-flops
are edge-triggered D-type flip-flops. On the
positive transition of the clock (CLK) input, the
device provides true data at the Q outputs.
A buffered output-enable (OE) input can be used
to place the ten outputs in either a normal logic
state (high or low level) or a high-impedance state.
In the high-impedance state, the outputs neither
load nor drive the bus lines significantly. The
high-impedance
state
and
increased
drive
provide the capability to drive bus lines without
interface or pullup components.
The output-enable (OE) input does not affect the internal operation of the flip-flops. Old data can be retained
or new data can be entered while the outputs are in the high-impedance state.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVC16821 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16821 is characterized for operation from − 40
°C to 85°C.
Copyright
 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
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1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
VCC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
VCC
2D7
2D8
GND
2D9
2D10
2CLK
EPIC and Widebus are trademarks of Texas Instruments Incorporated.


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