LC717A00AJ

No.A2089-4/11

I

*Not tested at low temperature before shipment

Parameter

Symbol

Pin Name

Conditions

min

typ

max

Unit

Remarks

SCL clock frequency

fSCL

SCL

400

kHz

START condition hold time

tHD;STA

SCL

SDA

0.6

μs

SCL clock low period

tLOW

SCL

1.3

μs

SCL clock high period

tHIGH

SCL

0.6

μs

Repeated START condition

setup time

tSU;STA

SCL

SDA

0.6

μs

*1

Data hold time

tHD;DAT

SCL

SDA

00.9

μs

Data setup time

tSU;DAT

SCL

SDA

100

μs

*1

SDA, SCL rise/fall time

tr / tf

SCL

SDA

300

μs

*1

STOP condition setup time

tSU;STO

SCL

SDA

0.6

μs

STOP-to-START bus release

time

tBUF

SCL

SDA

1.3

μs

*1

*

1) Design-guaranteed values (not tested before shipment)

SPI Bus Timing Characteristics

at VSS = 0, VDD = 2.6 to 5.5V, Ta = -40 to +105°C

*Not tested at low temperature before shipment

Parameter

Symbol

Pin Name

Conditions

min

typ

max

Unit

Remarks

SCK clock frequency

fSCK

SCK

5

MHz

SCK clock Low time

tLOW

SCK

90

ns

*1

SCK clock High time

tHIGH

SCK

90

ns

*1

Input signal rise/fall time

tr / tf

nCS

SCK

SI

300

ns

*1

nCS setup time

tSU;NCS

nCS

SCK

90

ns

*1

SCK clock setup time

tSU;SCK

nCS

SCK

90

ns

*1

Data setup time

tSU;SI

SCK

SI

20

ns

*1

Data hold time

tHD;SI

SCK

SI

30

ns

*1

nCS hold time

tHD;NCS

nCS

SCK

90

ns

*1

SCK clock hold time

tHD;SCK

nCS

SCK

90

ns

*1

nCS standby pulse width

tCPH

nCS

90

ns

*1

Output high impedance time

from nCS

tCHZ

nCS

SO

80

ns

*1

Output data determination time

tv

SCK

SO

80

ns

*1

Output data hold time

tHD;SO

SCK

SO

0

ns

*1

Output low impedance time

from SCK clock

tCLZ

SCK

SO

0

ns

*1

*

1) Design-guaranteed values (not tested before shipment)