AD1847

REV. B

–11–

Status Word (16-Bit)

Data 15

Data 14

Data 13

Data 12

Data 11

Data 10

Data 9

Data 8

res

res

RREQ

res

ID3

ID2

ID1

ID0

Data 7

Data 6

Data 5

Data 4

Data 3

Data 2

Data 1

Data 0

res

res

ORR1

ORR0

ORL1

ORL0

ACI

INIT

INIT

Initialization. This bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. INIT is

set HI on the last valid frame. It is reset LO for all other frames. Read by the host CPU or DSP from the AD1847.

The INIT bit is set HI on the last sample before the serial interface is inactivated. The only condition under which the

INIT bit is set is when a different sample rate is programmed. If FRS = 0 (32 slots per frame, two samples per frame)

and the sample rate is changed in the first sample of the 32 slot frame (i.e., during slots 0 through 15), the INIT bit will

be set on the second sample of that frame (i.e., during slots 16 through 31). If FRS = 0 and the sample rate is changed in

the second sample of the 32 slot frame, the INIT bit will be set on the second sample of the following frame.

ACI

Autocalibrate In-Progress. This bit indicates that autocalibration is in progress or the Mode Change Enable (MCE) state

has been recently exited. When exiting the MCE state with the ACAL bit set, the ACI bit will be set HI for 384 sample

periods. When exiting the MCE state with the ACAL bit reset, the ACAL bit will be set HI for 128 sample periods, indi-

cating that offset and filter values are being restored. Read by the host CPU or DSP from the AD1847.

0

Autocalibration not in progress

1

Autocalibration is in progress

ACI clear (i.e., reset or LO) should be recognized by first polling for a HI on the sample after the MCE bit is reset, and

then polling for a LO. Note that it is important not to start polling until one sample after MCE is reset, because if MCE

is set while ACI is HI, an ACI LO on the following sample will suggest a false clear of ACI.

ORL1:0

Overrange Left Detect. These bits indicate the overrange on the left input channel. Read by the host CPU or DSP from

the AD1847.

0

Greater than –1.0 dB underrange

1

Between –1.0 dB and 0 dB underrange

2

Between 0 dB and 1.0 dB overrange

3

Greater than 1.0 dB overrange

ORR1:0

Overrange Right Detect. These bits indicate the overrange on the right input channel. Read by the host CPU or DSP

from the AD1847.

0

Greater than –1.0 dB underrange

1

Between –1.0 dB and 0 dB underrange

2

Between 0 dB and 1.0 dB overrange

3

Greater than 1.0 dB overrange

ID3:0

AD1847 Revision ID. These four bits define the revision level of the AD1847. The first version of the AD1847 is desig-

nated ID = 0001. Read by the host CPU or DSP from the AD1847.

RREQ

This bit is reset LO for the Status Word, echoing the RREQ state written by the host CPU or DSP in the previous Con-

trol Word. Read by the host CPU or DSP from the AD1847.

res

Reserved for future expansion. All reserved bits read zero (LO).

Immediately after reset, the contents of this register is: 0000 0001 0000 0000 (0100h).