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AD5220BR10 датащит (PDF) 9 Page - Analog Devices

№ деталь AD5220BR10
подробность  Increment/Decrement Digital Potentiometer
скачать  12 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com

AD5220BR10 Datasheet(HTML) 9 Page - Analog Devices

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REV. 0
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A Terminal to +5 V and B Terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across terminals
AB divided by the 128-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to termi-
nals AB is:
VW(D) = D/128 × VAB + VB
D represents the current contents of the internal UP/DOWN
Operation of the digital potentiometer in the divider mode re-
sults in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value, therefore, the drift improves to 20 ppm/
The negative-edge sensitive CLK pin does not contain any
internal debounce circuitry. This standard CMOS logic input
responds to fast negative edges and needs to be debounced
externally with an appropriate circuit designed for the type of
switch closure device being used. Good performance results at
the CLK input pin when the negative logic transition has a
minimum slew rate of 1 V/
µs. A wide variety of standard circuits
can be used such as a one-shot multivibrator, Schmitt Triggered
gates, cross coupled flip-flops, or RC filters to drive the CLK
pin with uniform negative edges. This will prevent the digital
potentiometer from skipping output codes while counting due to
switch contact bounce.

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