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AD626AR-REEL7 датащи(PDF) 9 Page - Analog Devices |
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AD626AR-REEL7 датащи(HTML) 9 Page - Analog Devices |
9 / 12 page AD626 REV. C –9– 10 90 100 0% Figure 25. Settling Time. VS = +5 V, G = 10 10 90 100 0% Figure 26. Settling Time. VS = +5 V, G = 100 10k 10k 10k INPUT 20V p–p 1k +VS AD626 –VS ERROR OUT 2k Figure 27. Settling Time Test Circuit THEORY OF OPERATION The AD626 is a differential amplifier consisting of a precision balanced attenuator, a very low drift preamplifier (A1), and an output buffer amplifier (A2). It has been designed so that small differential signals can be accurately amplified and filtered in the presence of large common-mode voltages (VCM), without the use of any other active components. Figure 28 shows the main elements of the AD626. The signal inputs at Pins 1 and 8 are first applied to dual resistive attenuators R1 through R4 whose purpose is to reduce the peak common- mode voltage at the input to the preamplifier—a feedback stage based on the very low drift op amp A1. This allows the differen- tial input voltage to be accurately amplified in the presence of large common-mode voltages six times greater than that which can be tolerated by the actual input to A1. As a result, the input CMR extends to six times the quantity (VS – 1 V). The overall common-mode error is minimized by precise laser-trimming of R3 and R4, thus giving the AD626 a common-mode rejection ratio (CMRR) of at least 10,000:1 (80 dB). To minimize the effect of spurious RF signals at the inputs due to rectification at the input to A1, small filter capacitors C1 and C2 are included. AD626 C1 5pF +IN –IN R1 200k R2 200k R3 41k C2 5pF R4 41k R5 4.2k R11 10k R6 500 R7 500 R8 10k R10 10k R14 555 GND GAIN = 100 R13 10k R15 10k R17 95k R9 10k R12 100k FILTER OUT +VS A1 A2 –VS Figure 28. Simplified Schematic |
Аналогичный номер детали - AD626AR-REEL7 |
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Аналогичное описание - AD626AR-REEL7 |
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