поискавой системы для электроныых деталей |
|
AD6402 датащи(PDF) 6 Page - Analog Devices |
|
AD6402 датащи(HTML) 6 Page - Analog Devices |
6 / 8 page AD6402 –6– REV. 0 Demodulator Operation The PLL itself uses two loops: one for rapid frequency acquisi- tion and a second for demodulation. The first, or frequency- acquisition loop, locks the VCO to a noninteger multiple of the system clock, either 3/2 or 5/2 (using one fixed /2 and one pro- grammable /3 or /5 divider). This allows not only a choice of IF and system clocks but also prevents blocking of the receiver by keeping integer multiples of the system clock out of the IF passband. Once locked, this loop voltage is stored on an external capacitor and this sets the free-running frequency of the VCO during demodulation. The first loop is opened and, using the second loop and phase detector, the PLL compares the free-running frequency of its VCO to the frequency of the incoming IF. The VCO is then fast frequency locked, and slow phase locked to the incoming IF. Preconditioning of the PLL to the local reference clock facilitates the fast frequency lock to the received IF. The PLL now generates a baseband voltage proportional to the fre- quency deviation of the received signal. The demodulator uses a third-order PLL to track the incoming modulation signal. A simplified diagram of the demodulator is shown in Figures 3a and 3b. The loop bandwidth and damping factor can be adjusted by changing the values of C and R as indicated. An internal pole is present on the demodulator loop at approximately 9 MHz. For a loop ω n of 800 kHz, values of 910 pF and 330 Ω respectively are optimum. The loop band- width will approximately scale inversely as the square root of the value of C. To preserve a satisfactory damping factor, R should be adjusted linearly with the loop bandwidth. At low loop band- widths however the value of C offset must also be increased to enable the loop to lock to the reference frequency during prior to receive time slots. APPLICATIONS The AD6402 is optimized for use in applications where a data rate of the order of 1 megabit per second is required and the modulation scheme employed is constant envelope, i.e., FM or FSK. Because the demodulator uses a track and hold technique that locks to an externally supplied reference clock, the device is optimized for use in TDMA systems. If used in continuous demodulation applications, the dc offset hold voltage on the demodulator differential amplifier will ultimately leak away, resulting in the average dc value of the demodulator output eventually limiting against the supply rail. In a TDMA system, the voltage on the capacitor is refreshed just before the active PLLOUT COFF COFFSET 1.4k Ω 500 Ω 34pF VCO 220 A/RAD CFILT C R LIMITER Figure 3a. Demodulator Block Diagram (Lock Mode) COFF COFFSET CFILT C R CPUMP 14 A/RAD 34pF PD /3,/5 VCO /2 REFIN 160 A/RAD CPUMP Figure 3b. Demodulator Block Diagram (Dmod Mode) timeslot, thereby enabling a very accurate dc offset compensa- tion of system frequency errors. The on-chip IF filter has been designed to provide some rejec- tion of adjacent channel signals for channel bandwidths in the 1 MHz–2 MHz range. This filter has the benefit of reducing the contribution of broadband noise through the IF strip, hence improving the overall sensitivity of the receiver for a given demodulator output signal to noise ratio. It is also possible to use the AD6402 in applications where non- constant envelope modulation schemes are used, such as QPSK. In these applications the amplitude information will be lost through the limiting action of the IF strip, but in certain appli- cations, sufficient eye-opening will be observed in the demodu- lated signal to allow the use of hard decision bit-slicers as in the FM or FSK case. The actual performance of the subsystem in the presence of a QPSK signal will depend on factors such as bit rate, modulation index and BT employed. Figure 4 shows the RSSI response to a DECT signal at the IF port. It can be seen from the plot that the AD6402 can detect signals below –85 dBm and continues to detect linearly up to and above –5 dBm. INPUT POWER – dBm 1.6 0.6 0 –95 –91 –87 –75 –55 –35 –15 1.4 0.8 0.4 0.2 1.2 1.0 –3 1 Figure 4. RSSI Response Figure 5 shows an implementation for a DECT IF subsystem. DECT is a 1.152 megabit/second radio, employing Gaussian FSK modulation at a BT = 0.5 and uses a channel spacing of 1.728 MHz. It is a TDMA/TDD system. The IF frequency used in this application is 110.592 MHz. The AD6402’s flexible power management scheme enables the part to operate at low |
Аналогичный номер детали - AD6402 |
|
Аналогичное описание - AD6402 |
|
|
ссылки URL |
Конфиденциальность |
ALLDATASHEETRU.COM |
Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |