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AD73311L датащи(PDF) 10 Page - Analog Devices |
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AD73311L датащи(HTML) 10 Page - Analog Devices |
10 / 36 page REV. A AD73311L –10– FB = 4kHz FSINIT = DMCLK/8 a. Analog Antialias Filter Transfer Function FB = 4kHz FSINIT = DMCLK/8 SIGNAL TRANSFER FUNCTION NOISE TRANSFER FUNCTION b. Analog Sigma-Delta Modulator Transfer Function FB = 4kHz FSINTER = DMCLK/256 c. Digital Decimator Transfer Function FB = 4kHz FSFINAL = 8kHz FSINTER = DMCLK/256 d. Final Filter LPF (HPF) Transfer Function Figure 7. AD73311L ADC Frequency Responses Decimation Filter The digital filter used in the AD73311L carries out two impor- tant functions. Firstly, it removes the out-of-band quantization noise, which is shaped by the analog modulator and secondly, it decimates the high frequency bitstream to a lower rate 15-bit word. The antialiasing decimation filter is a sinc-cubed digital filter that reduces the sampling rate from DMCLK/8 at the modula- tor to an output rate at the SPORT of DMCLK/M (where M depends on the sample rate setting—M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and increases the resolution from a single bit to 15 bits. Its Z trans- form is given as: [(1–Z –N)/(1–Z–1)]3 where N is determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). This ensures a minimal group delay of 25 µs at the 64 kHz sampling rate. ADC Coding The ADC coding scheme is in twos complement format (see Figure 8). The output words are formed by the decimation filter, which grows the word length from the single-bit output of the sigma-delta modulator to a 15-bit word, which is the 16-bit transfer being used as a flag bit to indicate either control or data in the frame. VINN VINP VREF + (VREF 0.32875) VREF VREF – (VREF 0.32875) 10...00 00...00 01...11 ADC CODE DIFFERENTIAL VINN VINP VREF + (VREF 0.6575) VREF VREF – (VREF 0.6575) 10...00 00...00 01...11 ADC CODE SINGLE-ENDED ANALOG INPUT ANALOG INPUT Figure 8. ADC Transfer Function Decoder Channel The decoder channel consists of a digital interpolator, digital sigma-delta modulator, a single bit digital-to-analog converter (DAC), an analog smoothing filter and a programmable gain amplifier with differential output. DAC Coding The DAC coding scheme is in twos complement format with 0x7FFF being full-scale positive and 0x8000 being full-scale negative. Interpolation Filter The anti-imaging interpolation filter is a sinc-cubed digital filter which up-samples the 16-bit input words from the SPORT input rate of DMCLK/M (where M depends on the sample rate setting—M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while filtering to attenuate images produced by the interpolation pro- cess. Its Z transform is given as: [(1–Z –N)/(1–Z–1)]3 where N is determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @ 32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC receives 16-bit samples from the host DSP processor at a rate of DMCLK/M. If the host processor fails to write a new value to the serial port, the existing (previous) data is read again. The data stream is filtered by the anti-imaging interpolation filter, but there is an option to bypass the interpolator for the mini- mum group delay configuration by setting the IBYP bit (CRE:5) of Control Register E. The interpolation filter has the same charac- teristics as the ADC’s antialiasing decimation filter. |
Аналогичный номер детали - AD73311L |
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Аналогичное описание - AD73311L |
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