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AD7705BR датащи(PDF) 2 Page - Analog Devices

номер детали AD7705BR
подробное описание детали  3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD7705BR датащи(HTML) 2 Page - Analog Devices

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–2–
REV. A
AD7705/AD7706–SPECIFICATIONS (V
DD = +3 V or 5 V, REF IN(+) = +1.225 V with VDD = 3 V and +2.5 V
with VDD = 5 V; REF IN(–) = GND; MCLK IN = 2.4576 MHz unless otherwise noted. All specifications TMIN to TMAX unless otherwise noted.)
Parameter
B Version
1
Units
Conditions/Comments
STATIC PERFORMANCE
No Missing Codes
16
Bits min
Guaranteed by Design. Filter Notch < 60 Hz
Output Noise
See Tables I and III
Depends on Filter Cutoffs and Selected Gain
Integral Nonlinearity
2
±0.003
% of FSR max
Filter Notch < 60 Hz. Typically
±0.0003%
Unipolar Offset Error
See Note 3
Unipolar Offset Drift4
0.5
µV/°C typ
Bipolar Zero Error
See Note 3
Bipolar Zero Drift
4
0.5
µV/°C typ
For Gains 1, 2 and 4
0.1
µV/°C typ
For Gains 8, 16, 32, 64 and 128
Positive Full-Scale Error
5
See Note 3
Full-Scale Drift
4, 6
0.5
µV/°C typ
Gain Error7
See Note 3
Gain Drift
4, 8
0.5
ppm of FSR/
°C typ
Bipolar Negative Full-Scale Error
2
±0.003
% of FSR typ
Typically
±0.001%
Bipolar Negative Full-Scale Drift4
1
µV/°C typ
For Gains of 1 to 4
0.6
µV/°C typ
For Gains of 8 to 128
ANALOG INPUTS/REFERENCE INPUTS
Specifications for AIN and REF IN Unless Noted
Input Common-Mode Rejection (CMR)
2
VDD = 5 V
Gain = 1
96
dB typ
Gain = 2
105
dB typ
Gain = 4
110
dB typ
Gain = 8
v128
130
dB typ
VDD = 3 V
Gain = 1
105
dB typ
Gain = 2
110
dB typ
Gain = 4
120
dB typ
Gain = 8
v128
130
dB typ
Normal-Mode 50 Hz Rejection
2
98
dB typ
For Filter Notches of 25 Hz, 50 Hz,
±0.02 × f
NOTCH
Normal-Mode 60 Hz Rejection
2
98
dB typ
For Filter Notches of 20 Hz, 60 Hz,
±0.02 × f
NOTCH
Common-Mode 50 Hz Rejection
2
150
dB typ
For Filter Notches of 25 Hz, 50 Hz,
±0.02 × f
NOTCH
Common-Mode 60 Hz Rejection
2
150
dB typ
For Filter Notches of 20 Hz, 60 Hz,
±0.02 × f
NOTCH
Absolute/Common-Mode REF IN Voltage
2
GND to VDD
V min to V max
Absolute/Common-Mode AIN Voltage
2, 9
GND – 30 mV
V min
BUF Bit of Setup Register = 0
VDD + 30 mV
V max
Absolute/Common-Mode AIN Voltage
2, 9
GND + 50 mV
V min
BUF Bit of Setup Register = 1
VDD – 1.5 V
V max
AIN DC Input Current
2
1
nA max
AIN Sampling Capacitance
2
10
pF max
AIN Differential Voltage Range
10
0 to +VREF/GAIN
11
nom
Unipolar Input Range (B/U Bit of Setup Register = 1)
±V
REF/GAIN
nom
Bipolar Input Range (B/U Bit of Setup Register = 0)
AIN Input Sampling Rate, fS
GAIN
× f
CLKIN/64
For Gains of 1 to 4
fCLKIN/8
For Gains of 8 to 128
Reference Input Range
REF IN(+) – REF IN(–) Voltage
1/1.75
V min/max
VDD = 2.7 V to 3.3 V. VREF = 1.225 ± 1% for Specified
Performance
REF IN(+) – REF IN(–) Voltage
1/3.5
V min/max
VDD = 4.75 V to 5.25 V. VREF = 2.5 ± 1% for Specified
Performance
REF IN Input Sampling Rate, fS
fCLKIN/64
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
±1
µA max
Typically
±20 nA
MCLK
±10
µA max
Typically
±2 µA
All Inputs Except SCLK and MCLK IN
VINL, Input Low Voltage
0.8
V max
VDD = 5 V
0.4
V max
VDD = 3 V
VINH, Input High Voltage
2.0
V min
VDD = 3 V and 5 V
SCLK Only (Schmitt Triggered Input)
VDD = 5 V NOMINAL
VT+
1.4/3
V min/V max
VT–
0.8/1.4
V min/V max
VT+ – VT–
0.4/0.8
V min/V max
SCLK Only (Schmitt Triggered Input)
VDD = 3 V NOMINAL
VT+
1/2.5
V min/V max
VT–
0.4/1.1
V min/V max
VT+ – VT–
0.375/0.8
V min/V max
MCLK IN Only
VDD = 5 V NOMINAL
VINL, Input Low Voltage
0.8
V max
VINH, Input High Voltage
3.5
V min
MCLK IN Only
VDD = 3 V NOMINAL
VINL, Input Low Voltage
0.4
V max
VINH, Input High Voltage
2.5
V min


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