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AD7711AAR датащи(PDF) 6 Page - Analog Devices

номер детали AD7711AAR
подробное описание детали  LC2MOS Signal Conditioning ADC with RTD Current Source
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD7711AAR датащи(HTML) 6 Page - Analog Devices

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REV. C
AD7711A
–6–
Limit at TMIN, TMAX
Parameter
(A, S Versions)
Units
Conditions/Comments
External Clocking Mode
fSCLK
fCLK IN/5
MHz max
Serial Clock Input Frequency
t20
0
ns min
DRDY to RFS Setup Time
t21
0
ns min
DRDY to RFS Hold Time
t22
2
× t
CLK IN
ns min
A0 to
RFS Setup Time
t23
0
ns min
A0 to
RFS Hold Time
t24
7
4
× t
CLK IN
ns max
Data Access Time (
RFS Low to Data Valid)
t25
7
10
ns min
SCLK Falling Edge to Data Valid Delay
2
× t
CLK IN + 20
ns max
t26
2
× t
CLK IN
ns min
SCLK High Pulsewidth
t27
2
× t
CLK IN
ns min
SCLK Low Pulsewidth
t28
tCLK IN + 10
ns max
SCLK Falling Edge to
DRDY High
t29
8
10
ns min
SCLK to Data Valid Hold Time
tCLK IN + 10
ns max
t30
10
ns min
RFS/TFS to SCLK Falling Edge Hold Time
t31
8
5
× t
CLK IN/2 + 50
ns max
RFS to Data Valid Hold Time
t32
0
ns min
A0 to
TFS Setup Time
t33
0
ns min
A0 to
TFS Hold Time
t34
4
× t
CLK IN
ns min
SCLK Falling Edge to
TFS Hold Time
t35
2
× t
CLK IN – SCLK High
ns min
Data Valid to SCLK Setup Time
t36
30
ns min
Data Valid to SCLK Hold Time
NOTES
1Guaranteed by design, not production tested. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 10 to 13.
3The AD7711A is specified with a 10 MHz clock for AV
DD voltages of +5 V
± 5%. It is specified with an 8 MHz clock for AV
DD voltages greater than 5.25 V and less
than 10.5 V.
4CLK IN duty cycle range is 45% to 55%. CLK IN must be supplied whenever the AD7711A is not in STANDBY mode. If no clock is present in this case, the device
can draw higher current than specified and possibly become uncalibrated.
5The AD7711A is production tested with f
CLK IN at 10 MHz (8 MHz for AVDD > +5.25 V). It is guaranteed by characterization to operate at 400 kHz.
6Specified using 10% and 90% points on waveform of interest.
7These numbers are measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V.
8These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then
extrapolated back to remove effects of charging or discharging the 100 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
Specifications subject to change without notice.
TO OUTPUT
PIN
100pF
200 A
1.6mA
+2.1V
Figure 1. Load Circuit for Access Time and Bus Relinquish
Time
PIN CONFIGURATION
DIP and SOIC
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
16
15
14
13
1
2
3
4
5
6
7
8
9
10
11
12
AD7711A
AVDD
VSS
AIN1(–)
SCLK
MCLK IN
MCLK OUT
A0
AIN1(+)
MODE
SYNC
VBIAS
REF IN(–)
REF IN(+)
REF OUT
RTD CURRENT
DGND
DVDD
SDATA
DRDY
AGND
TFS
RFS
AIN2(–)
AIN2(+)


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