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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD7851ARS датащи(PDF) 4 Page - Analog Devices |
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AD7851ARS датащи(HTML) 4 Page - Analog Devices |
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4 / 36 page  AD7851 –4– REV. A Limit at TMIN, TMAX Parameter A, K Units Description fCLKIN 2 500 kHz min Master Clock Frequency 7 MHz max fSCLK 3 10 MHz max Interface Modes 1, 2, 3 (External Serial Clock) fCLK IN MHz max Interface Modes 4, 5 (Internal Serial Clock) t1 4 100 ns min CONVST Pulse Width t2 50 ns max CONVST ↓ to BUSY↑ Propagation Delay tCONVERT 3.25 µs max Conversion Time = 20 tCLKIN t3 –0.4 tSCLK ns min SYNC ↓ to SCLK↓ Setup Time (Noncontinuous SCLK Input) ±0.4 t SCLK ns min/max SYNC ↓ to SCLK↓ Setup Time (Continuous SCLK Input) t4 0.6 tSCLK ns min SYNC ↓ to SCLK↓ Setup Time. Interface Mode 4 Only t5 5 30 ns max Delay from SYNC ↓ until DOUT 3-State Disabled t5A 5 30 ns max Delay from SYNC ↓ until DIN 3-State Disabled t6 5 45 ns max Data Access Time After SCLK ↓ t7 30 ns min Data Setup Time Prior to SCLK ↑ t8 20 ns min Data Valid to SCLK Hold Time t9 6 0.4 tSCLK ns min SCLK High Pulse Width (Interface Modes 4 and 5) t10 6 0.4 tSCLK ns min SCLK Low Pulse Width (Interface Modes 4 and 5) t11 30 ns min SCLK ↑ to SYNC↑ Hold Time (Noncontinuous SCLK) 30/0.4 tSCLK ns min/max (Continuous SCLK) Does Not Apply to Interface Mode 3 t11A 50 ns max SCLK ↑ to SYNC↑ Hold Time t12 7 50 ns max Delay from SYNC ↑ until DOUT 3-State Enabled t13 90 ns max Delay from SCLK ↑ to DIN Being Configured as Output t14 8 50 ns max Delay from SCLK ↑ to DIN Being Configured as Input t15 2.5 tCLKIN ns max CAL ↑ to BUSY↑ Delay t16 2.5 tCLKIN ns max CONVST ↓ to BUSY↑ Delay in Calibration Sequence tCAL 9 41.7 ms typ Full Self-Calibration Time, Master Clock Dependent (250026 tCLKIN) tCAL1 9 37.04 ms typ Internal DAC Plus System Full-Scale Cal Time, Master Clock Dependent (222228 tCLKIN) tCAL2 9 4.63 ms typ System Offset Calibration Time, Master Clock Dependent (27798 tCLKIN) tDELAY 65 ns max Delay from CLK to SCLK NOTES Descriptions that refer to SCLK ↑ (rising) or SCLK↓ (falling) edges here are with the POLARITY pin HIGH. For the POLARITY pin LOW then the opposite edge of SCLK will apply. 1Sample tested at +25 °C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V. See Table X and timing diagrams for different interface modes and calibration. 2Mark/Space ratio for the master clock input is 40/60 to 60/40. 3For Interface Modes 1, 2, 3 the SCLK max frequency will be 10 MHz. For Interface Modes 4 and 5 the SCLK will be an output and the frequency will be f CLKIN. 4The CONVST pulse width will here only apply for normal operation. When the part is in power-down mode, a different CONVST pulse width will apply (see Power- Down section). 5Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.4 V. 6For self-clocking mode (Interface Modes 4, 5) the nominal SCLK high and low times will be 0.5 t SCLK = 0.5 tCLKIN. 7t 12 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 12, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. 8t 14 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true delay of the part in turning off the output drivers and configuring the DIN line as an input. Once this time has elapsed the user can drive the DIN line knowing that a bus conflict will not occur. 9The typical time specified for the calibration times is for a master clock of 6 MHz. Specifications subject to change without notice. TIMING SPECIFICATIONS1 (AV DD = DVDD = +5.0 V 5%; fCLKIN = 6 MHz, TA = TMIN to TMAX, unless otherwise noted) |
Аналогичный номер детали - AD7851ARS |
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Аналогичное описание - AD7851ARS |
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