AD809

REV. A

–4–

DEFINITION OF TERMS

Maximum, Minimum and Typical Specifications

Specifications for every parameter are derived from statistical

analyses of data taken on multiple devices from multiple wafer

lots. Typical specifications are the mean of the distribution of

the data for that parameter. If a parameter has a maximum (or a

minimum), that value is calculated by adding to (or subtracting

from) the mean six times the standard deviation of the distribu-

tion. This procedure is intended to tolerate production varia-

tions: if the mean shifts by 1.5 standard deviations, the remaining

4.5 standard deviations still provide a failure rate of only 3.4

parts per million. For all tested parameters, the test limits are

guardbanded to account for tester variation to thus guarantee

that no device is shipped outside of data sheet

specifications.

Capture and Tracking Range

This is the range of input data rates over which the AD809 will

remain in lock.

Jitter

This is the dynamic displacement of digital signal edges from

their long term average positions, measured in degrees rms.

Jitter on the input clock causes jitter on the synthesized clock.

Output Jitter

This is the jitter on the synthesized clock (OUTPUT, OUTPUT),

in degrees rms.

Jitter Transfer

The AD809 exhibits a low-pass filter response to jitter applied

to its input data.

Bandwidth

This describes the frequency at which the AD809 attenuates

sinusoidal input jitter by 3 dB.

Peaking

This describes the maximum jitter gain of the AD809 in dB.

Damping Factor,

Damping factor,

ζ describes the compensation of the second or-

der PLL. A larger value of

ζ corresponds to more damping and

less peaking in the jitter transfer function.

Duty Cycle Tolerance

The AD809 exhibits a duty cycle tolerance that is measured

by applying an input signal (nominal input frequency) with a

known duty cycle imbalance and measuring the

×8 or ×16

output frequency.

Symmetry-Recovered Clock Duty Cycle

Symmetry is calculated as (100

× on time)/period, where on time

equals the time that the clock signal is greater than the midpoint

between its “0” level and its “1” level.

Typical Characteristic Curves

RMS JITTER – Degrees

1200

1000

0

More

1.8

800

600

400

200

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4

100

90

80

70

60

50

40

30

20

10

0

AD809 FREQUENCY SYNTHESIZER

JITTER DISTRIBUTION MATRIX

75 DEVICES (3 LOTS)

[ECL, TTL]

× [×8, ×16] × [RISE, FALL] × [+4.5V, +5.0V, +5.5V] × [–40°C, +25°C, +85°C]

THIS CHART DESCRIBES THE

AD809 OUTPUT JITTER

SPECIFICATION OVER MANY

CONDITIONS. THE DATA

REPRESENTED ARE TAKEN

WITH RESPECT TO THE RISING

AND FALLING EDGES, FOR

EACH FREQUENCY RANGE,

LOCKED TO EITHER TTL OR

ECL INPUT, OVER ALL

TEMPERATURE AND SUPPLY

CONDITIONS.

0.0

FREQUENCY

CUMULATIVE %

Figure 2. Jitter Histogram

INPUT DUTY CYCLE – %

1.9

1.3

1.0

0

100

10

20

30

40

50

60

70

80

90

1.8

1.2

1.1

1.6

1.4

1.7

1.5

19.44MHz

9 72MHz

Figure 3. Jitter vs. Input Duty Cycle