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ADV7202 датащи(PDF) 9 Page - Analog Devices |
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ADV7202 датащи(HTML) 9 Page - Analog Devices |
9 / 26 page REV. PrB PRELIMINARY TECHNICAL DATA ADV7202 –9– PIN FUNCTION DESCRIPTIONS Input/ Pin No. Mnemonic Output Function 1 SYNC_IN I This signal can be used to synchronize the updating of clamps. Polarity is pro- grammable via I 2C or SPI. 2 CLK/SCK I MPU Port Serial Interface Clock Input. If the SPI interface is enabled, this pin is clock input. If the I 2C interface is enabled, this pin is SCK. 3 LE/ALSB I If the SPI interface is enabled, this pin is Latch Enable. If the I 2C interface is en- abled, this pin is the ALSB Address Select Pin. This signal sets up the LSB of the MPU address. MPU address = 2cH, ALSB = 0, MPU address = 2eH, ALSB = 1. When this pin is tied high, the I 2C filter is activated, which reduces noise on the I 2C interface. When this pin is tied low, the input bandwidth on the I2C lines is increased. 4 XTAL0 I Input Terminal for crystal oscillator or connection for external oscillator with CMOS-compatible square wave clock signal. 5 XTAL1 O Second Terminal for Crystal Oscillator. Not connected if external clock source is used. 6 AVDD_ADC P ADC Analog Supply Voltage (5 V or 3.3 V) 7 AVSS_ADC G Ground for ADC Analog Supply 8–19 AIN1–6 I Analog Signal Inputs. Can be configured differentially or single-ended. 20 SPI_SEL I A high signal on the pin selects SPI MPU port serial operation; a low signal selects I2C MPU port serial operation. 21 REFADC I/O Internally generated Voltage Reference or programmable reference out. 22 CML O Common-Mode Level for ADCs 23, 24 CAP2, CAP1 I ADC Capacitor Network 25 OSDEN I Enable data from OSDIN0–2 to be switched to the outputs when set to a logic high. 26–35 DOUT[9:0] O ADC data output 36 OSDIN2 I Third Input Channel for On-Screen Display 37 OSDIN1 I Second Input Channel for On-Screen Display 38 OSDIN0 I First Input Channel for On-Screen Display 39 DAC3_OUT O General Purpose Analog Output 40 DAC2_OUT O Analog Output. Can Be Used to Output CVBS, R or U 41 AVSS_DAC G Ground for DAC Analog Supply 42 AVDD_DAC P DAC Analog Supply Voltage (5 V or 3.3 V) 43 DAC1_OUT O Analog Output. Can Be Used to Output CVBS, Y, G, or Luma. 44 DAC0_OUT O Analog Output. Can Be Used to Output CVBS, V, B, or Chroma. 45 COMP O Compensation Pin for DACs. Connect 0.1 µF capacitor from COMP pin to AVDD_DAC. 46 VREFDAC I/O DAC Voltage Reference Output Pin, Nominally 1.235 V. Can be driven by an external voltage reference. 47 RSET I Used to control the amplitude of the DAC output current, 1200 Ω gives an I max of 4.33 µA. 48 RESET I Master Reset (Asynchronous) 49–52, 55, 56, DAC_DATA[9:0] I DAC Input Data for Four Video Rate DACs 59–62 53 DVSS G Ground for Digital Core Supply 54 DVDD P Analog Supply Voltage for Digital Core (5 V or 3.3 V) 57, 58 DAC_CLK[1:0] I DAC Clocks 63 SYNC_OUT O Output Sync Signal, which goes to a high state while Cr data sample from a YCrCb data stream or C data from a Y/C data stream is output on DOUT[9:0]. 64 SI_SDA I/O If the SPI interface is enabled, this pin is serial data In. If the I2C interface is enabled, this pin is MPU Port Serial Data Input/Output. |
Аналогичный номер детали - ADV7202 |
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Аналогичное описание - ADV7202 |
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