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FW804 датащи(PDF) 8 Page - Agere Systems |
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FW804 датащи(HTML) 8 Page - Agere Systems |
8 / 24 page 88 Agere Systems Inc. Data Sheet, Rev. 3 June 2001 Four-Cable Transceiver/Arbiter Device FW804 PHY IEEE 1394A Signal Information (continued) Table 1. Signal Descriptions (continued) Pin Signal* Type Name/Description 19 LPS I Link Power Status. LPS is connected to either the VDD supplying the LLC or to a pulsed output that is active when the LLC is powered for the purpose of monitoring the LLC power status. If LPS is inactive for more than 1.2 µs and less than 25 µs, interface is reset. If LPS is inactive for greater than 25 µs, the PHY will disable the PHY/Link interface to save power. FW804 continues its repeater function. 1LREQ I Link Request. LREQ is an output from the LLC that requests the PHY to perform some service. Bus-keeper circuitry is built into this terminal. 9, 31, 71, 72 NC — No Connect. 23 PC0 I Power-Class Indicators. On hardware reset, these inputs set the default value of the power class indicated during self-ID. These bits can be programmed by tying the signals to VDD (high) or to ground (low). 24 PC1 25 PC2 18 PD I Powerdown. When asserted high, PD turns off all internal circuitry except the bias-detect circuits that drive the CNA signal. 73 PLLVDD — Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry portion of the device. 74, 75 PLLVSS — Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground plane. 66 R0 I Current Setting Resistor. An internal reference voltage is applied to a resistor connected between R0 and R1 to set the operating current and the cable driver output current. A low temperature-coefficient resistor (TCR) with a value of 2.49 k Ω ± 1% should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. 67 R1 78 /RESET I Reset (Active-Low). When /RESET is asserted low (active), the FW804 is reset. An internal pull-up resistor, which is connected to VDD, is provided, so only an external delay capacitor is required to ensure that the capacitor is discharged when PHY power is removed. This input is a standard logic buffer and can also be driven by an open-drain logic output buffer. 32 SE I Test Mode Control. SE is used during the manufacturing test and should be tied to VSS. 33 SM I Test Mode Control. SM is used during the manufacturing test and should be tied to VSS. 2 SYSCLK O System Clock. SYSCLK provides a 49.152 MHz clock signal, which is synchronized with the data transfers to the LLC. 45 TPA0+ Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted- pair cable. Board traces from each pair of positive and negative differen- tial signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 52 TPA1+ 58 TPA2+ 39 TPA3+ 44 TPA0 − Analog I/O Portn, Port Cable Pair A. TPAn is the port A connection to the twisted- pair cable. Board traces from each pair of positive and negative differen- tial signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. 51 TPA1 − 57 TPA2 − 38 TPA3– * Active-low signals are indicated by “/” at the beginning of signal names, within this document. |
Аналогичный номер детали - FW804 |
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Аналогичное описание - FW804 |
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