© 2000 Fairchild Semiconductor Corporation

DS006429

www.fairchildsemi.com

August 1986

Revised March 2000

DM74LS367A

Hex 3-STATE Buffer/Bus Driver

General Description

This device contains six independent gates each of which

performs a non-inverting buffer function. The outputs have

the 3-STATE feature. When enabled, the outputs exhibit

the low impedance characteristics of a standard LS output

with additional drive capability to permit the driving of bus

lines without external resistors. When disabled, both the

output transistors are turned OFF presenting a high-imped-

ance state to the bus line. Thus the output will act neither

as a significant load nor as a driver. To minimize the possi-

bility that two outputs will attempt to take a common bus to

opposite logic levels, the disable time is shorter than the

enable time of the outputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Y

= A

H

= HIGH Logic Level

L

= LOW Logic Level

X

= Either LOW or HIGH Logic Level

Hi-Z

= 3-STATE (Outputs are disabled)

Order Number

Package Number

Package Description

DM74LS367AM

M16A

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS367AN

N16E

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Inputs

Output

AG

Y

LL

L

HL

H

X

H

Hi-Z