PLL Frequency Synthesizer

ADF4108S

ASD0016548

Rev.A

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R COUNTER

The 14-bit R counter allows the input reference frequency to be divided down to produce the reference clock to the phase

frequency detector (PFD). Division ratios from 1 to 16,383 are allowed.

PHASE FREQUENCY DETECTOR AND CHARGE PUMP

The phase frequency detector (PFD) takes inputs from the R counter and N counter (N = BP + A) and produces an output

proportional to the phase and frequency difference between them. Figure 7 is a simplified schematic. The PFD includes a

programmable delay element that controls the width of the antibacklash pulse. This pulse ensures that there is no dead

zone in the PFD transfer function and minimizes phase noise and reference spurs. Two bits in the reference counter latch,

ABP2 and ABP1, control the width of the pulse (see Figure 10). Use of the minimum antibacklash pulse width is not

recommended.

Figure 7. PFD Simplified Schematic and Timing (in Lock)

MUXOUT AND LOCK DETECT

The output multiplexer on the ADF4108 allows the user to access various internal points on the chip. The state of MUXOUT

is controlled by M3, M2, and M1 in the function latch. Figure 11 shows the full truth table. Figure 8 shows the MUXOUT

section in block diagram form.

Lock Detect

MUXOUT can be programmed for two types of lock detect: digital lock detect and analog lock detect.

Digital lock detect is active high. When the lock detect precision (LDP) bit in the R counter latch is set to 0, digital lock detect

is set high when the phase error on three consecutive phase detector (PD) cycles is less than 15 ns. With LDP set to 1, five

consecutive cycles of less than 15 ns are required to set the lock detect. It stays set high until a phase error of greater than

25 ns is detected on any subsequent PD cycle.

The N-channel open-drain analog lock detect should be operated with an external pull-

up resistor of 10 kΩ nominal. When

lock has been detected, this output is high with narrow, low going pulses.