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AD7706BRU датащи(PDF) 6 Page - Analog Devices |
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AD7706BRU датащи(HTML) 6 Page - Analog Devices |
6 / 44 page AD7705/AD7706 Rev. C | Page 6 of 44 Parameter B Version1 Unit Conditions/Comments AIN Input Sampling Rate, fS Gain × fCLKIN/64 For gains of 1 to 4 fCLKIN/8 For gains of 8 to 128 Reference Input Range REF IN(+) − REF IN(−) Voltage 1/1.75 V min/V max VDD = 2.7 V to 3.3 V VREF = 1.225 ± 1% for specified performance REF IN(+) − REF IN(−) Voltage 1/3.5 V min/V max VDD = 4.75 V to 5.25 V VREF = 2.5 ± 1% for specified performance REF IN Input Sampling Rate, fS fCLKIN/64 LOGIC INPUTS Input Current All Inputs, Except MCLK IN ±1 μA max Typically ±20 nA MCLK IN ±10 μA max Typically ±2 μA All Inputs, Except SCLK and MCLK IN Input Low Voltage, VINL 0.8 V max VDD = 5 V 0.4 V max VDD = 3 V Input High Voltage, VINH 2.0 V min VDD = 3 V and 5 V SCLK Only (Schmitt-Triggered Input) VDD = 5 V nominal VT+ 1.4/3 V min/V max VT− 0.8/1.4 V min/V max VT+ − VT− 0.4/0.8 V min/V max SCLK Only (Schmitt-Triggered Input) VDD = 3 V nominal VT+ 1/2 V min/V max VT− 0.4/1.1 V min/V max VT+ − VT− 0.375/0.8 V min/V max MCLK IN Only VDD = 5 V nominal Input Low Voltage, VINL 0.8 V max Input High Voltage, VINH 3.5 V min MCLK IN Only VDD = 3 V nominal Input Low Voltage, VINL 0.4 V max Input High Voltage, VINH 2.5 V min LOGIC OUTPUTS (Including MCLK OUT) Output Low Voltage, VOL 0.4 V max ISINK = 800 μA, except for MCLK OUT;13 VDD = 5 V Output Low Voltage, VOL 0.4 V max ISINK = 100 μA, except for MCLK OUT;13 VDD = 3 V Output High Voltage, VOH 4 V min ISOURCE = 200 μA, except for MCLK OUT;13 VDD = 5 V Output High Voltage, VOH VDD − 0.6 V min ISOURCE = 100 μA, except for MCLK OUT;13 VDD = 3 V Floating State Leakage Current ±10 μA max Floating State Output Capacitance14 9 pF typ Data Output Coding Binary Unipolar mode Offset binary Bipolar mode SYSTEM CALIBRATION Positive Full-Scale Limit15 (1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Negative Full-Scale Limit15 −(1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Offset Limit15 −(1.05 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) Input Span16 (0.8 × VREF)/gain V min Gain is the selected PGA gain (1 to 128) (2.1 × VREF)/gain V max Gain is the selected PGA gain (1 to 128) |
Аналогичный номер детали - AD7706BRU |
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Аналогичное описание - AD7706BRU |
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