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AD7608BSTZ датащи(PDF) 11 Page - Analog Devices |
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AD7608BSTZ датащи(HTML) 11 Page - Analog Devices |
11 / 32 page Data Sheet AD7608 Rev. A | Page 11 of 32 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD7608 TOP VIEW (Not to Scale) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PIN 1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AGND AVCC 1 3 4 FRSTDATA 7 6 5 OS 2 2 8 9 10 12 13 14 15 16 11 DB0 BUSY CONVST B CONVST A RANGE RESET RD/SCLK CS PAR/SER SEL OS 1 OS 0 STBY DECOUPLING CAPACITOR PIN DATA OUTPUT POWER SUPPLY ANALOG INPUT GROUND PIN DIGITAL OUTPUT DIGITAL INPUT REFERENCE INPUT/OUTPUT DB15 REFIN/REFOUT 48 46 45 42 43 44 47 41 40 39 37 36 35 34 33 38 AGND AVCC REFGND REFCAPA AGND AGND AGND REFCAPB REFGND REGCAP REGCAP AVCC AVCC REF SELECT Figure 7. Pin Configuration Table 6. Pin Function Descriptions Pin No. Type 12F11F 1 Mnemonic Description 1, 37, 38, 48 P AVCC Analog Supply Voltage 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end amplifiers and to the ADC core. These supply pins should be decoupled to AGND. 2, 26, 35, 40, 41, 47 P AGND Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7608. All analog input signals and external reference signals should be referred to these pins. All six of these AGND pins should connect to the AGND plane of a system. 5, 4, 3 DI OS [2: 0] Oversampling Mode Pins. Logic inputs. These inputs are used to select the oversampling ratio. OS 2 is the MSB control bit, while OS 0 is the LSB control bit. See the Digital Filter section for further details on the oversampling mode of operation and Table 8 for oversampling bit decoding. 6 DI AA PAREE AA /SER SEL Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. In serial mode, the AA RDEE AA /SCLK pin functions as the serial clock input. The DB7/DOUTA and DB8/DOUTB pins function as serial data outputs. When the serial interface is selected, DB[15:9] and DB[6:0] pins should be tied to GND. 7 DI AA STBYEE Standby Mode Input. This pin is used to place the AD7608 into one of two power-down modes: standby mode or shutdown mode. The power-down mode entered depends on the state of the RANGE pin as shown in Table 7. When in standby mode, all circuitry, except the on-chip reference regulators, and regulator buffers, is powered down. When in shutdown mode, all circuitry is powered down. 8 DI RANGE Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic change on this pin has an immediate effect on the analog input range. Changing this pin during a conversion is not recommended. See the Analog Input section for more details. 9, 10 DI CONVST A, CONVST B Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A and CONVST B can be shorted together and a single convert start signal applied. Alternatively, CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and CONVST B can be used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and V8). This is only possible when oversampling is not switched on. When the CONVST A or CONVST B pin transitions from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to hold. This function allows a phase delay to be created inherently between the sets of analog inputs. |
Аналогичный номер детали - AD7608BSTZ |
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Аналогичное описание - AD7608BSTZ |
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