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MKL14Z32VFM4 датащи(PDF) 26 Page - Freescale Semiconductor, Inc |
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MKL14Z32VFM4 датащи(HTML) 26 Page - Freescale Semiconductor, Inc |
26 / 47 page Table 12. MCG specifications (continued) Symbol Description Min. Typ. Max. Unit Notes fdco_t_DMX32 DCO output frequency Low range (DRS = 00) 732 × ffll_ref — 23.99 — MHz 5, 6 Mid range (DRS = 01) 1464 × ffll_ref — 47.97 — MHz Jcyc_fll FLL period jitter • fVCO = 48 MHz — 180 — ps 7 tfll_acquire FLL target frequency acquisition time — — 1 ms 8 PLL fvco VCO operating frequency 48.0 — 100 MHz Ipll PLL operating current • PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 48) — 1060 — µA 9 Ipll PLL operating current • PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref = 2 MHz, VDIV multiplier = 24) — 600 — µA 9 fpll_ref PLL reference frequency range 2.0 — 4.0 MHz Jcyc_pll PLL period jitter (RMS) • fvco = 48 MHz • fvco = 100 MHz — — 120 50 — — ps ps 10 Jacc_pll PLL accumulated jitter over 1µs (RMS) • fvco = 48 MHz • fvco = 100 MHz — — 1350 600 — — ps ps 10 Dlock Lock entry frequency tolerance ± 1.49 — ± 2.98 % Dunl Lock exit frequency tolerance ± 4.47 — ± 5.97 % tpll_lock Lock detector detection time — — 150 × 10-6 + 1075(1/ fpll_ref) s 11 1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock mode). 2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft. 3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0. 4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation ( Δfdco_t) over voltage and temperature must be considered. 5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1. 6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device. 7. This specification is based on standard deviation (RMS) of period or frequency. 8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed, DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running. 9. Excludes any oscillator currents that are also consuming power while PLL is in operation. 10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of each PCB and results will vary. 11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes it is already running. Peripheral operating requirements and behaviors KL14 Sub-Family Data Sheet Data Sheet, Rev. 3, 9/19/2012. 26 Freescale Semiconductor, Inc. |
Аналогичный номер детали - MKL14Z32VFM4 |
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Аналогичное описание - MKL14Z32VFM4 |
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