Intel

R

Datasheet Addendum

9

2.4.

Signal Groups

To ease discussion of the AC and DC characteristics, the signals on the GMCH have been combined into

groups with similar characteristics. These signal groups are referenced throughout this document.

Table 2. GMCH Signal Groups

Signal

Group

Signal Type

Signals

(a)

GTL+ I/O

HA[31:3]#, HD[63:0]#, ADS#, BNR#, DBSY#, DRDY#, HIT#, HITM#,

HREQ[4:0]#, HTRDY#, RS[2:0]#

(b)

GTL+ Input

HLOCK#

(c)

GTL+ Output

CPURST#, BPRI#, DEFER#

(d)

GTL+ Termination Voltage

GTLREF[B:A]

(e)

CMOS (2.5V) Input

HCLK

(f)

CMOS I/O

SDQM[7:0], SMD[63:0], LMD[31:0], LDQM[3:0]

(g)

CMOS Input

SCLK, RESET#, DCLKREF, LRCLK

(h)

CMOS Output

SCS[3:0]#, SRAS#, SCAS#, SMAA[11:0], SBS[1:0], SMAB[7:4]#,

SWE#, SCKE[1:0], LCS#, LSRAS#, LSCAS#, LMA [11:0], LWE#,

LOCLK, LTCLK

(k)

CMOS (1.8V) Input

TVCLKIN/INT#

(l)

CMOS (1.8V) Output

CLKOUT[1:0], BLANK#, LTVDATA[11:0], TVVSYNC, TVHSYNC

(m)

CMOS I/OD

DDCSCL*, DDCSDA*, LTVCL, LTVDA

(n)

RAMDAC output

RED, GREEN, BLUE

(o)

Display Sync output

VSYNC, HSYNC

(p)

Display Reference

IREF, IWASTE

NOTES:

1. DDC inputs are not 5V tolerant.