AD6620AS datasheet(1/44 Pages) AD

номер детали	AD6620AS

подробное описание детали	67 MSPS Digital Receive Signal Processor

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REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties that

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

a

AD6620

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

www.analog.com

Fax: 781/326-8703

67 MSPS Digital Receive

Signal Processor

FUNCTIONAL BLOCK DIAGRAM

REAL,

DUAL REAL,

OR COMPLEX

INPUTS

SERIAL OR

PARALLEL

OUTPUTS

CIC

FILTERS

OUTPUT

FORMAT

COMPLEX

NCO

P

OR SERIAL

CONTROL

I

Q

–SIN

COS

EXTERNAL

SYNC

CIRCUITRY

JTAG

PORT

II

QQ

FIR

FILTER

AD6620

FEATURES

High Input Sample Rate

67 MSPS Single Channel Real

33.5 MSPS Diversity Channel Real

33.5 MSPS Single Channel Complex

NCO Frequency Translation

Worst Spur Better than –100 dBc

Tuning Resolution Better than 0.02 Hz

2nd Order Cascaded Integrator Comb FIR Filter

Linear Phase, Fixed Coefficients

Programmable Decimation Rates: 2, 3 . . . 16

5th Order Cascaded Integrator Comb FIR Filter

Linear Phase, Fixed Coefficients

Programmable Decimation Rates: 1, 2, 3 . . . 32

Programmable Decimating RAM Coefficient FIR Filter

Up to 134 Million Taps per Second

256 20-Bit Programmable Coefficients

Programmable Decimation Rates: 1, 2, 3 . . . 32

Bidirectional Synchronization Circuitry

Phase Aligns NCOs

Synchronizes Data Output Clocks

Serial or Parallel Baseband Outputs

Pin Selectable Serial or Parallel

Serial Works with SHARC

®, ADSP-21xx, Most Other

DSPs

16-Bit Parallel Port, Interleaved I and Q Outputs

Two Separate Control and Configuration Ports

Generic

P Port, Serial Port

3.3 V Optimized CMOS Process

JTAG Boundary Scan

GENERAL DESCRIPTION

The AD6620 is a digital receiver with four cascaded signal-

processing elements: a frequency translator, two fixed-

coefficient decimating filters, and a programmable coefficient

decimating filter. All inputs are 3.3 V LVCMOS compatible.

All outputs are LVCMOS and 5 V TTL compatible.

As ADCs achieve higher sampling rates and dynamic range, it

becomes increasingly attractive to accomplish the final IF stage

of a receiver in the digital domain. Digital IF Processing is less

expensive, easier to manufacture, more accurate, and more

flexible than a comparable highly selective analog stage.

The AD6620 diversity channel decimating receiver is designed

to bridge the gap between high-speed ADCs and general pur-

pose DSPs. The high resolution NCO allows a single carrier to

be selected from a high speed data stream. High dynamic range

decimation filters with a wide range of decimation rates allow

both narrowband and wideband carriers to be extracted. The

RAM-based architecture allows easy reconfiguration for multi-

mode applications.

The decimating filters remove unwanted signals and noise from

the channel of interest. When the channel of interest occupies

less bandwidth than the input signal, this rejection of out-of-

band noise is called “processing gain.” By using large decimation

factors, this “processing gain” can improve the SNR of the

ADC by 36 dB or more. In addition, the programmable RAM

Coefficient filter allows antialiasing, matched filtering, and

static equalization functions to be combined in a single, cost-

effective filter.

The input port accepts a 16-bit Mantissa, a 3-bit Exponent,

and an A/B Select pin. These allow direct interfacing with the

AD6600, AD6640, AD6644, AD9042 and most other high-

speed ADCs. Three input modes are provided: Single Channel

Real, Single Channel Complex, and Diversity Channel Real.

When paired with an interleaved sampler such as the AD6600,

the AD6620 can process two data streams in the Diversity

Channel Real input mode. Each channel is processed with coher-

ent frequency translation and output sample clocks. In addition,

external synchronization pins are provided to facilitate coherent

frequency translation and output sample clocks among several

AD6620s. These features can ease the design of systems with

diversity antennas or antenna arrays.

Units are packaged in an 80-lead PQFP (plastic quad flatpack)

and specified to operate over the industrial temperature range

(–40

°C to +85°C).

SHARC is a registered trademark of Analog Devices, Inc.

Аналогичный номер детали - AD6620AS

производитель	номер детали	датащи	подробное описание детали
Analog Devices	AD6620AS	354Kb / 43P	65 MSPS Digital Receive Signal Processor REV. 0
	AD6620AS	374Kb / 44P	67 MSPS Digital Receive Signal Processor REV. A
	AD6620ASZ	374Kb / 44P	67 MSPS Digital Receive Signal Processor REV. A

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Аналогичное описание - AD6620AS

производитель	номер детали	датащи	подробное описание детали
Analog Devices	AD6620ASZ	374Kb / 44P	67 MSPS Digital Receive Signal Processor REV. A
	AD6620	399Kb / 44P	67 MSPS Digital Receive Signal Processor REV. A
	AD6620	354Kb / 43P	65 MSPS Digital Receive Signal Processor REV. 0
	AD6624	566Kb / 40P	Four-Channel, 80 MSPS Digital Receive Signal Processor REV. B
	AD6624A	642Kb / 40P	Four-Channel, 100 MSPS Digital Receive Signal Processor REV. 0
	AD6624	509Kb / 40P	Four-Channel, 80 MSPS Digital Receive Signal Processor (RSP) REV. B
	AD6624A	636Kb / 40P	Four-Channel, 100 MSPS Digital Receive Signal Processor (RSP) REV. 0
	AD6634	931Kb / 52P	80 MSPS, Dual-Channel WCDMA Receive Signal Processor REV. 0
	AD6635	805Kb / 60P	4-Channel, 80 MSPS WCDMA Receive Signal Processor REV. 0
	AD6634	925Kb / 52P	80 MSPS, Dual-Channel WCDMA Receive Signal Processor (RSP) REV. 0

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