ML2035

REV. 1.0 10/10/2000

7

SERIAL DIGITAL INTERFACE

The digital interface consists of a shift register and data

latch. The serial 16-bit data word on SID is clocked into a

16-bit shift register on rising edges of the serial shift clock,

SCK. The LSB should be shifted in first and the MSB last as

shown in Figure 4. The data that has been shifted into the

shift register is loaded into a 16-bit data latch on the

falling edge of LATI. To insure that true data is loaded into

the data latch from the shift register, LATI falling edge

should occur when SCK is low, as shown in figure 1. LATI

should be low while shifting data into the shift register to

avoid inadvertently entering the power down mode. Note

that all data is entered and latched on the edges, not

levels, of SCK and LATI.

POWER DOWN MODE

The power down mode of the ML2035 can be selected by

entering all zeros in the shift register and applying a logic

“1” to LATI and holding it high. A zero data detect circuit

detects when all bits in the shift register are zeros. In this

state, the power consumption is reduced to 11.5mW max,

10k

Ω to ground. The master clock, CLK IN, can be left

active or removed during power down mode.

Figure 4. Serial Interface Timing.

SCK

SID

LATI

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Figure 5. Power Down Mode Waveforms.

POWER SUPPLIES

It is recommended that the power supplies to the device

should be bypassed by placing decoupling capacitors

the device as possible.

0V

POWER DOWN MODE

SCK

SID

LATI

01234567 89 10 11 12 131415