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AD9255BCPZ-80 датащи(PDF) 1 Page - Analog Devices

номер детали AD9255BCPZ-80
подробное описание детали  14-Bit, 125 MSPS/105 MSPS/80 MSPS
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9255BCPZ-80 датащи(HTML) 1 Page - Analog Devices

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14-Bit, 125 MSPS/105 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
Data Sheet
AD9255
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2009–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
FEATURES
SNR = 78.3 dBFS at 70 MHz and 125 MSPS
SFDR = 93 dBc at 70 MHz and 125 MSPS
Low power: 371 mW at 125 MSPS
1.8 V analog supply operation
1.8 V CMOS or LVDS output supply
Integer 1-to-8 input clock divider
IF sampling frequencies to 300 MHz
−153.4 dBm/Hz small signal input noise with 200 Ω input
impedance at 70 MHz and 125 MSPS
Optional on-chip dither
Programmable internal ADC voltage reference
Integrated ADC sample-and-hold inputs
Flexible analog input range: 1 V p-p to 2 V p-p
Differential analog inputs with 650 MHz bandwidth
ADC clock duty cycle stabilizer
Serial port control
User-configurable, built-in self-test (BIST) capability
Energy-saving power-down modes
APPLICATIONS
Communications
Multimode digital receivers (3G)
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and
TD-SCDMA
Smart antenna systems
General-purpose software radios
Broadband data applications
Ultrasound equipment
PRODUCT HIGHLIGHTS
1.
On-chip dither option for improved SFDR performance
with low power analog input.
2.
Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3.
Operation from a single 1.8 V supply and a separate digital
output driver supply accommodating 1.8 V CMOS or
LVDS outputs.
4.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary, twos complement, or gray coding), enabling
the clock DCS, power-down, test modes, and voltage
reference mode.
5.
Pin compatibility with the AD9265, allowing a simple
migration up to 16 bits.
FUNCTIONAL BLOCK DIAGRAM
14
14
DRVDD (1.8V)
D13 TO D0
OEB
DCO
DITHER
CLK+
CLK–
SYNC
CLOCK
MANAGEMENT
ADC
14-BIT
CORE
OUTPUT
STAGING
CMOS OR
LVDS
(DDR)
VCM
VREF
VIN+
VIN–
TRACK-AND-HOLD
REFERENCE
RBIAS
SENSE
PDWN
SERIAL PORT
SVDD SCLK/
DFS
SDIO/
DCS
CSB
AGND
AVDD (1.8V)
LVDS LVDS_RS
AD9255
OR
Figure 1.


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