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AD8174AR датащи(PDF) 8 Page - Analog Devices |
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AD8174AR датащи(HTML) 8 Page - Analog Devices |
8 / 16 page AD8170/AD8174 –8– REV. 0 THEORY OF OPERATION General The AD8170/AD8174 multiplexers integrate wideband analog switches with a high speed current feedback amplifier. The input switches are complementary bipolar follower stages that are turned on and off by using a current steering technique that attains switch times of less than 10 ns and ensures low switching transients. The 250 MHz current feedback amplifier provides up to 50 mA of drive current. Overall gain and frequency response are set by external resistors for maximum versatility. Figure 22 is a block diagram of the multiplexer signal chain, with a simplified schematic of an input switch. When the channel is on (i.e., VONB more positive than VREFB, VONT more negative than VREFT), I2 flows through Q1 and Q2, and I3 flows through Q3 and Q4. This biases up Q5 through Q8 to form the unity gain follower. I1 and I4 (the “off” currents) are steered, either to another switch or to the power supply. When the channel turns off, I2 and I3 are steered away while I1 switches over to pull the base of Q8 up to VCLT + 1 VBE (about 2.7 volts from ground reference) and I4 switches over to pull the base of Q5 down to VCLB – 1 VBE (about –2.7 volts away from ground reference). Clamping the bases of the reverse biased output transistors to a low impedance point greatly improves isolation performance. The AD8174 has four switches with outputs wired together and driving the positive input of a current feedback amplifier to form a 4:1 multiplexer. It is designed so that only one channel is on at a time. By bringing ENABLE high, the supply current for the amplifier is shut off. This turns the output of the amplifier into a high impedance, allowing the AD8174 to be used in larger arrays. In practice, the disabled output impedance of the mux will be determined by the amplifier’s feedback network. Bringing SD high shuts off the supply current for all the switches, that some of the logic control circuitry and the amplifier, reducing the quiescent current drain to 1.5 mA. If the ENABLE and SD functions are not to be used, those respective pins must be tied to ground for proper operation. Any unused channel input should also be tied to ground. The AD8170 has two switches driving an amplifier to form a 2:1 multiplexer. No disable or shutdown functions are provided. DC Performance and Noise Considerations Figure 23 shows the different contributors to total output offset and noise. Total expected output offset can be calculated using Equation 1 below: VOS out ()= I B+ × RS ()+V OS [] 1+RF RG + IB− × RF () (1) VOS/Ven IB+/Ien+ RS VIN SWITCH BUFFER IB–/Ien– RF RG VOUT Figure 23. DC Errors for Buffered Multiplexer Equations 2 and 3 below can be used to predict the output voltage noise of the multiplexer for different choices of gains and external resistors. The different contributions to output noise are root-sum-squared to calculate total output noise spectral density in Equation 2. As there is no peaking in the multiplier’s noise characteristic, the total peak-to-peak output noise will be accurately predicted using Equation 3. V EN (OUT ) nV / Hz ()= I EN + × RS ()2+ V EN ()2 1 + RF RG 2 + I EN – × R F ()2+4KT R F + RS 1 + RF RG 2 + R G RF RG 2 (2) V EN p−p =V EN × f −3dB × 6.2 ×1.26 (3) VOUT VFB I6 I3 VCLB VONT VREFT VOFFB VREFB VOFFT VREFT I1 VONB VREFB I4 I2 VCLT IN0 IN1 IN2 IN3 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Figure 22. Block Diagram and Simplified Schematic of the AD8170 |
Аналогичный номер детали - AD8174AR |
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Аналогичное описание - AD8174AR |
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