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AD9884A/PCB датащи(PDF) 9 Page - Analog Devices |
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AD9884A/PCB датащи(HTML) 9 Page - Analog Devices |
9 / 24 page REV. C AD9884A –9– Table III. Default Register Values Reg Value Reg Value 00 01101001 69h 08 10000000 80h 01 1101 0000 D0h 09 10000000 80h 02 10000000 80h 0A 11110100 F4h 03 10000000 80h 0B 10000 000 80h 04 10000000 80h 0C 0 01 001 00 24h 05 100000 00 80h 0D 00000000 00h 06 100000 00 80h 0E 0000xxx0 0xh 07 100000 00 80h 0F 00000000 00h CONTROL REGISTER DETAIL PLL DIVIDER CONTROL 00 7–0 PLLDIVM PLL Divide Ratio MSBs The eight most significant bits of the 12-bit PLL divide ratio PLLDIV. The operational divide ratio is PLLDIV + 1. The PLL derives a master clock from an incoming HSYNC signal. The master clock frequency is then divided by an integer value, and the divider’s output is phase-locked to HSYNC. This PLLDIV value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. This is typically 20% to 30% more than the number of active pixels in the display. The 12-bit value of PLLDIV supports divide ratios from 2 to 4095. The higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed HSYNC frequency. VESA has established some standard timing specifications, which will assist in determining the value for PLLDIV as a function of horizontal and vertical display resolution and frame rate (Table VII). However, many computer systems do not conform precisely to the recommendations, and these numbers should be used only as a guide. The display system manufacturer should provide auto- matic or manual means for optimizing PLLDIV. An incorrectly set PLLDIV will usually produce one or more vertical noise bars on the display. The greater the error, the greater the number of bars produced. The power-up default value of PLLDIV is 1693 (PLLDIVM = 69h, PLLDIVL = Dxh). 01 7–4 PLLDIVL PLL Divide Ratio LSBs The four least significant bits of the 12-bit PLL divide ratio PLLDIV. The operational divide ratio is PLLDIV + 1. The power-up default value of PLLDIV is 1693 (PLLDIVM = 69h, PLLDIVL = Dxh). CONTROL REGISTER MAP The AD9884A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to write and read the control registers through the 2-line serial interface port. Table II. Control Register Map Reg Bit Default Mnemonic Function PLL Divider Control 00 7–0 01101001 PLLDIVM PLL Divide Ratio MSBs 01 7–4 1101 •••• PLLDIVL PLL Divide Ratio LSBs 01 3–0 ••••0000 Reserved, Set to Zero Input Gain 02 7–0 10000000 REDGAIN Red Channel Gain Adjust 03 7–0 10000000 GRNGAIN Green Channel Gain Adjust 04 7–0 10000000 BLUGAIN Blue Channel Gain Adjust Input Offset 05 7–2 100000 •• REDOFST Red Channel Offset Adjust 05 1–0 ••••••00 Reserved, Set to Zero 06 7–2 100000 •• GRNOFST Green Channel Offset Adjust 06 1–0 ••••••00 Reserved, Set to Zero 07 7–2 100000 •• BLUOFST Blue Channel Offset Adjust 07 1–0 ••••••00 Reserved, Set to Zero Clamp Timing 08 7–0 10000000 CLPLACE Clamp Placement 09 7–0 10000000 CLDUR Clamp Duration General Control 1 0A 7 1 ••••••• DEMUX Output Port Select 0A 6 •1•••••• PAR Output Timing Select 0A 5 ••1••••• HSPOL HSYNC Polarity 0A 4 •••1•••• CSTPOL COAST Polarity 0A 3 ••••0••• EXTCLMP Clamp Signal Source 0A 2 •••••1•• CLAMPOL Clamp Signal Polarity 0A 1 ••••••0• EXTCLK External Clock Select 0A 0 •••••••0 Reserved, Set to Zero Clock Generator Control 0B 7–3 10000 ••• PHASE Clock Phase Adjust 0B 2–0 •••••000 Reserved, Set to Zero 0C 7 0 ••••••• Reserved, Set to Zero 0C 6–5 •01••••• VCORNGE VCO Range Select 0C 4–2 •••001•• CURRENT Charge Pump Current 0C 1–0 ••••••00 Reserved, Set to Zero General Control 2 0D 7–5 000 ••••• Reserved, Set to Zero 0D 4 •••0•••• OUTPHASE Output Port Phase 0D 3–1 ••••000• REVID Die Revision ID 0D 0 •••••••0 Reserved, Set to Zero 0E 7–0 00000000 Reserved, Set to Zero |
Аналогичный номер детали - AD9884A/PCB |
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Аналогичное описание - AD9884A/PCB |
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