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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD73360ASU датащи(PDF) 6 Page - Analog Devices |
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AD73360ASU датащи(HTML) 6 Page - Analog Devices |
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6 / 35 page  REV. A AD73360 –6– TIMING CHARACTERISTICS Limit at Parameter TA = –40 C to +85 C Unit Description Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t1 ns min SCLK Width High t6 0.4 × t 1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK (AVDD = 3 V 10%; DVDD = 3 V 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) TIMING CHARACTERISTICS Limit at Parameter TA = –40 C to +85 C Unit Description Clock Signals See Figure 1 t1 61 ns min MCLK Period t2 24.4 ns min MCLK Width High t3 24.4 ns min MCLK Width Low Serial Port See Figures 3 and 4 t4 t1 ns min SCLK Period t5 0.4 × t 1 ns min SCLK Width High t6 0.4 × t1 ns min SCLK Width Low t7 20 ns min SDI/SDIFS Setup Before SCLK Low t8 0 ns min SDI/SDIFS Hold After SCLK Low t9 10 ns max SDOFS Delay from SCLK High t10 10 ns min SDOFS Hold After SCLK High t11 10 ns min SDO Hold After SCLK High t12 10 ns max SDO Delay from SCLK High t13 30 ns max SCLK Delay from MCLK (AVDD = 5 V 10%; DVDD = 5 V 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless otherwise noted) |
Аналогичный номер детали - AD73360ASU |
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Аналогичное описание - AD73360ASU |
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