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AD5024 датащи(PDF) 6 Page - Analog Devices |
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AD5024 датащи(HTML) 6 Page - Analog Devices |
6 / 24 page AD5512A/AD5542A Rev. A | Page 6 of 24 TIMING CHARACTERISTICS VDD = 5 V, 2.5 V ≤ VREF ≤ VDD, VINH = 90% of VLOGIC, VINL = 10% of VLOGIC, AGND = DGND = 0 V, unless otherwise noted. Table 5. Parameter1, 2 Limit 1.8 ≤ VLOGIC ≤ 2.7 V3 Limit 2.7 V ≤ VLOGIC ≤ 5.5 V4 Unit Description fSCLK 14 50 MHz max SCLK cycle frequency t1 70 20 ns min SCLK cycle time t2 35 10 ns min SCLK high time t3 35 10 ns min SCLK low time t4 5 5 ns min CS low to SCLK high setup t5 5 5 ns min CS high to SCLK high setup t6 5 5 ns min SCLK high to CS low hold time t7 10 5 ns min SCLK high to CS high hold time t8 35 10 ns min Data setup time t9 5 4 ns min Data hold time (VINH = 90% of VDD, VINL = 10% of VDD) t9 5 5 ns min Data hold time (VINH = 3 V, VINL = 0 V) t10 20 20 ns min LDAC pulsewidth t11 10 10 ns min CS high to LDAC low setup t12 15 15 ns min CS high time between active periods t13 15 15 ns CLR pulsewidth 1 Guaranteed by design and characterization, not production tested. 2 All input signals are specified with tR = tF = 1 ns/V and timed from a voltage level of (VINL + VINH)/2. 3 −40°C < TA < +105°C. 4 −40°C < TA < +125°C. SCLK CS DIN DB151 DB112 LDAC t6 t4 t12 t8 t9 t2 t3 t1 t7 t5 t11 t10 CLR t13 NOTES 1. FOR AD5542A = DB15. 2. FOR AD5512A = DB11. Figure 3. Timing Diagram |
Аналогичный номер детали - AD5024 |
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Аналогичное описание - AD5024 |
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