TPS2390

TPS2391

SLUS471D − JUNE 2002 − REVISED JANUARY 2008

11

www.ti.com

APPLICATION INFORMATION

UDG−02091

+

+

40mV

30 V

99

R

R

+

+

+

+

SQ

Q

R

FAULT

LOGIC

100mV

SLOW

0.5V

4V

LCA

1.4V

VDD

50

µA

ON

TIMER

BLOCK

’91 ONLY

RAMP

CONTROL

EN_A

OC

OVERLOAD

COMP

4

8

2

5

3

1

6

7GATE

ISENS

FAULT

FLTTIME

IRAMP

RTN

EN

−VIN

DCHG

RETRY

ON

14V

VDD

10

µA

600 nA

0.4

µA

OL

ON

Figure 17. Block Diagram

Fault timing is accomplished by connecting a capacitor between the FLTTIME and −VIN pins, allowing

user-programming of the timeout period. Whenever the hot swap controller is in current control mode as

described above, the LCA asserts an overcurrent indication (OC in the Figure 17 diagram). Overcurrent fault

timing is inhibited during the slow turn-on portion of the IRAMP waveform. However, once the device transitions

generating a voltage ramp at the FLTTIME pin. If this voltage reaches the 4-V fault threshold, the fault is latched,

and the open-drain driver is turned on to assert the external FAULT output. Fault capacitor charging ceases,

and the capacitor is now discharged. In addition, latching of a fault condition causes rapid discharge of the

IRAMP capacitor. In this manner, the soft-start function is now reset and ready for the next output enable, if and

when conditions permit.

The TPS2390 latches off in response to faults; once a fault timeout occurs, the discharge signal (DCHG) turns

on a large NMOS device to rapidly discharge the external capacitor, resetting the timer for any subsequent

device reset. The TPS2390 can only be reset by cycling power to the device, or by cycling the EN input.