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ADF4153YCPZ датащи(PDF) 5 Page - Analog Devices |
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ADF4153YCPZ датащи(HTML) 5 Page - Analog Devices |
5 / 24 page Data Sheet ADF4153 Rev. F | Page 5 of 24 Parameter B Version1 Y Version2 Unit Test Conditions/Comments NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH)5 −220 −220 dBc/Hz typ PLL loop BW = 500 kHz Normalized 1/f Noise (PN1_f)6 −114 −114 dBc/Hz typ Measured at 10 kHz offset, normalized to 1 GHz Phase Noise Performance7 @ VCO output 1750 MHz Output8 −102 −102 dBc/Hz typ @ 5 kHz offset, 25 MHz PFD frequency 1 Operating temperature for B version is −40°C to +85°C. 2 Operating temperature for Y version is −40°C to +125°C. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N). 6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 7 The phase noise is measured with the EV-ADF4153SD1Z and the Agilent E5500 phase noise system. 8 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode. TIMING SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 20 ns min LE setup time t2 10 ns min DATA to CLK setup time t3 10 ns min DATA to CLK hold time t4 25 ns min CLK high duration t5 25 ns min CLK low duration t6 10 ns min CLK to LE setup time t7 20 ns min LE pulse width CLK DATA LE LE DB23 (MSB) DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t1 t2 t3 t7 t6 t4 t5 Figure 2. Timing Diagram |
Аналогичный номер детали - ADF4153YCPZ |
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Аналогичное описание - ADF4153YCPZ |
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