Data Sheet

ADF4153

Rev. F | Page 5 of 24

Parameter

B Version1

Y Version2

Unit

Test Conditions/Comments

NOISE CHARACTERISTICS

Normalized Phase Noise Floor

−220

−220

dBc/Hz typ

PLL loop BW = 500 kHz

−114

−114

dBc/Hz typ

Measured at 10 kHz offset, normalized to 1 GHz

Phase Noise Performance7

@ VCO output

1750 MHz Output8

−102

−102

dBc/Hz typ

@ 5 kHz offset, 25 MHz PFD frequency

1

Operating temperature for B version is −40°C to +85°C.

2

Operating temperature for Y version is −40°C to +125°C.

3

4

Guaranteed by design. Sample tested to ensure compliance.

5

The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider

6

7

The phase noise is measured with the EV-ADF4153SD1Z and the Agilent E5500 phase noise system.

8

TIMING SPECIFICATIONS

dBm referred to 50 Ω.

Table 2.

Parameter

Unit

Test Conditions/Comments

20

ns min

LE setup time

10

ns min

DATA to CLK setup time

10

ns min

DATA to CLK hold time

25

ns min

CLK high duration

25

ns min

CLK low duration

10

ns min

CLK to LE setup time

20

ns min

LE pulse width

CLK

DATA

LE

LE

DB23 (MSB)

DB22

DB2

DB1

(CONTROL BIT C2)

DB0 (LSB)

(CONTROL BIT C1)

Figure 2. Timing Diagram