A(18:0)

Latter of E1Z

low of E2 high

DQ(31:0)

MBE

Data valid

Data valid

t

, t

ETQV

ETMV

t

, t

ETQX

ETMX

Assumptions: GZ low, WZ high and SCRUBZ high. Reading uninitialized addresses will cause

MBE to be asserted.

A(18:0)

DQ(31:0)

MBE

Previous valid data

Valid data

Valid data

t

, t

AXQX

AXMX

t

, t

AVQV1

AVMV

Assumptions: E1Z low, E2 high, WZ high, GZ low and SCRUBZ high. Reading uninitialized addresses will

cause MBE to be asserted.

SMV512K32-SP

SLVSA21H – JUNE 2011 – REVISED JULY 2013

www.ti.com

Table 4. AC Characteristics Read Cycle (1) (continued)

SYMBOL

PARAMETER

MIN

MAX

UNIT

FIGURE

GZ-controlled error flag valid

8.6

ns

Figure 6

GZ-controlled error flag enable time

3.5

ns

Figure 6

E-controlled error flag enable time

3.5

ns

Figure 5

E-controlled error flag time

20

ns

Figure 5

(3)

GZ-controlled error flag tri-state time

3.5

5

ns

Figure 6

(3)

Chip enable change to MBE tri-state

3.5

5

ns

Figure 5

(3)

Parameters ensured by design and/or characterization if not production tested.

Figure 4. SRAM Read Cycle 1, Address-Controlled Access

Figure 5. Read Cycle 2, Chip Enable-Controlled Access

8

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