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AM79C32A датащи(PDF) 8 Page - Advanced Micro Devices

номер детали AM79C32A
подробное описание детали  Digital Subscriber Controller??(DSC?? Circuit
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производитель  AMD [Advanced Micro Devices]
домашняя страница  http://www.amd.com
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AM79C32A датащи(HTML) 8 Page - Advanced Micro Devices

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Am79C30A/32A Data Sheet
OPERATIONAL DESCRIPTION
Overview of Power Modes
The minimization of power consumption is a key factor
in the design of Terminal Equipment for the ISDN, and
the DSC/IDC circuit employs two basic approaches to
power management:
1. The power consumption of the DSC/IDC circuit it-
self is managed by using four basic power modes
which allow unused functional blocks to be dis-
abled. The INIT register may be programmed to se-
lect Active Voice and Data, Active Data Only, Idle, or
Power-Down mode, depending upon which DSC/
IDC device resources are required at the time.
2. The power consumption of the controlling micro-pro-
cessor system may be controlled by driving the pro-
cessor clock with the DSC/IDC circuit MCLK output.
A wide range of MCLK operating frequencies may be
selected, and a special Clock Speed-Up function is
provided which increases the speed of MCLK upon
the occurrence of a key event, without processor in-
tervention. Control of MCLK frequency and Clock
Speed-up is accomplished by programming the INIT
and INIT2 registers, as described later.
Active Voice and Data Mode
In Active Voice and Data mode all functional blocks of
the DSC/IDC circuit are available. Device registers may
be accessed through the MPI, the LIU and DLC are
available, the OSC is running, the Peripheral Port is
available, MUX connections may be made, the Sec-
ondary Tone Ringer may be activated, and the MAP is
operational (DSC circuit only).
Active Data Only Mode
Active Data Only mode is similar to Active Voice and
Data mode, except that the MAP (DSC circuit only) is
disabled to reduce system power consumption. This in-
creases the amount of power available for the Second-
ary Tone Ringer or microprocessor system during the
phases of call setup and teardown, or during a
data-only telephone call.
Idle Mode
Idle mode is the RESET default mode of DSC/IDCcir-
cuit operation, and represents an operational state in
which power consumption is reduced, yet the micropro-
cessor system is operational to program DSC/IDC cir-
cuit registers or perform other required background
tasks. Idle mode may also be entered by appropriate
programming of the INIT register.
In Idle mode, the MCLK output is available to drive the
microprocessor system, the MPI is available for pro-
gramming of DSC/IDC registers, and the LIU is avail-
able to initiate or respond to S/T interface activity. The
HSW hookswitch interrupt is also available in Idle mode.
Idle mode reduces DSC/IDC circuit power consump-
tion by disabling the MUX, DLC, and MAP functional
blocks. The Peripheral Port is also disabled, except that
an IOM-2 activation request interrupt is possible, and
the SFS and SCLK outputs may still be activated. The
SFS and SCLK outputs are high impedance upon RE-
SET, but become active after any MUX connection is
programmed. The DLC read-only registers are cleared
when the DSC/IDC circuit enters the Idle mode.
Power-Down Mode
Power-Down mode consumes the least power of all the
DSC/IDC power options, and differs from Idle mode in
that all clocks, including the XTAL oscillator, are
stopped. Most functional blocks are disabled, except
for those required to recognize key external events that
will force the DSC/IDC circuit to return to Idle mode.
The Power-Down mode is not available unless the
Power-Down Enable bit is set in the INIT2 register; see
the INIT2 register description for further details.
Entering the Power-Down Mode
The Power-Down mode is entered by appropriate pro-
gramming of the INIT and INIT2 registers. Selection of
the Power-Down mode causes the DSC/IDCcircuit to
begin an internal countdown of at least 250 MCLK cy-
cles after which the MCLK and XTAL1 outputs are both
stopped and held High, and the XTAL2input will be dis-
regarded. The purpose of this countdown cycle is to
allow the microprocessor time for housekeeping oper-
ations before its clock is stopped. If an interrupt causes
the DSC INT pin to go Low during the countdown, the
Power-Down mode bits in the INIT register will be reset
and the countdown will be canceled.
If the LIU is enabled and in any state other than F3 at
the end of the countdown, MCLK is stopped but the os-
cillator continues to run. This allows the LIU to identify
the incoming signal and either (1) generate an interrupt
and force the DSC/IDC circuit to Idle mode when acti-
vation is complete, or (2) move to the F3 state and stop
the oscillator once the line goes idle.
Exiting the Power-Down Mode
The DSC/IDC circuit will exit the Power-Down mode
and enter the Idle mode if any of the following events
occur:
The DSC/IDC circuit receives a hardware reset via
the RESET pin.
•The CS and WR pins are both pulled Low at the
same time, as would occur during a normal write
operation from the microprocessor to the DSC cir-
cuit. No data will be transferred by this operation.
The HSW hookswitch pin changes state, and the
hookswitch interrupt is enabled.


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